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authorJonathan Neuschäfer <j.neuschaefer@gmx.net>2018-10-01 09:45:49 +0200
committerRonald G. Minnich <rminnich@gmail.com>2018-10-06 21:30:32 +0000
commit50b74b2a270b85bdd843dd7925c21596534f07b3 (patch)
tree35ed9b36d7eb86a81384057ac3cd1d0fa0bf3feb /src/arch
parent5fba1ea5bcb4c804fe40bfe7da9cf8681ab806eb (diff)
downloadcoreboot-50b74b2a270b85bdd843dd7925c21596534f07b3.tar.xz
arch/riscv: Update comment about mstatus initialization
coreboot does not set up virtual memory anymore. Change-Id: I231af07b2988e8362d1cdd606ce889fb31136ff1 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/28831 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/riscv/bootblock.S2
-rw-r--r--src/arch/riscv/ramstage.S2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/riscv/bootblock.S b/src/arch/riscv/bootblock.S
index 95e1923ce2..277c3910c0 100644
--- a/src/arch/riscv/bootblock.S
+++ b/src/arch/riscv/bootblock.S
@@ -66,7 +66,7 @@ _hart_zero:
# clear any pending interrupts
csrwi mip, 0
- # set up the mstatus register for VM
+ # set up the mstatus register
call mstatus_init
tail main
diff --git a/src/arch/riscv/ramstage.S b/src/arch/riscv/ramstage.S
index 906215ca01..c721a126c4 100644
--- a/src/arch/riscv/ramstage.S
+++ b/src/arch/riscv/ramstage.S
@@ -43,7 +43,7 @@ _start:
csrwi mip, 0
call exit_car
- # set up the mstatus register for VM
+ # set up the mstatus register
call mstatus_init
tail main