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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-09 11:41:15 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-15 05:32:44 +0000
commit544878b56349a74e8cb7a0e9af899b5f7fc246fc (patch)
tree0a586dcbe6e70c94be6b7d123f43dd7c294dad68 /src/arch
parent5bc641afebda5fd274ba713add4145651d9bc71d (diff)
downloadcoreboot-544878b56349a74e8cb7a0e9af899b5f7fc246fc.tar.xz
arch/x86: Add postcar_frame_common_mtrrs()
As most platforms will share the subset of enabling both low RAM WB and high ROM WP MTRRs, provide them with a single function. Add possibility for the platform to skip these if required. Change-Id: Id1f8b7682035e654231f6133a42909a36e3e15a1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34809 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/x86/include/arch/cpu.h6
-rw-r--r--src/arch/x86/postcar_loader.c12
2 files changed, 18 insertions, 0 deletions
diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h
index 606202197e..9aa446ec0a 100644
--- a/src/arch/x86/include/arch/cpu.h
+++ b/src/arch/x86/include/arch/cpu.h
@@ -302,6 +302,7 @@ struct postcar_frame {
uint32_t upper_mask;
int max_var_mtrrs;
int num_var_mtrrs;
+ int skip_common_mtrr;
};
/*
@@ -323,6 +324,11 @@ void postcar_frame_add_mtrr(struct postcar_frame *pcf,
void postcar_frame_add_romcache(struct postcar_frame *pcf, int type);
/*
+ * Add a common MTRR setup most platforms will have as a subset.
+ */
+void postcar_frame_common_mtrrs(struct postcar_frame *pcf);
+
+/*
* Push used MTRR and Max MTRRs on to the stack
* and return pointer to stack top.
*/
diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c
index 35e139fe1c..b1b2da0540 100644
--- a/src/arch/x86/postcar_loader.c
+++ b/src/arch/x86/postcar_loader.c
@@ -120,6 +120,18 @@ void postcar_frame_add_romcache(struct postcar_frame *pcf, int type)
postcar_frame_add_mtrr(pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE, type);
}
+void postcar_frame_common_mtrrs(struct postcar_frame *pcf)
+{
+ if (pcf->skip_common_mtrr)
+ return;
+
+ /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
+ postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
+
+ /* Cache the ROM as WP just below 4GiB. */
+ postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT);
+}
+
void *postcar_commit_mtrrs(struct postcar_frame *pcf)
{
/*