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authorIonela Voinescu <ionela.voinescu@imgtec.com>2015-07-24 15:00:20 +0100
committerMartin Roth <martinroth@google.com>2015-12-29 18:02:15 +0100
commite7a336ac29b1ef5aaa1b0aa4926ed75829b491b1 (patch)
tree7dbee4b28e86cf01de98498bf06fb4c4f3e92fae /src/arch
parentc2b51085ca4aa3427ad788e9b402e0da46a0b1a6 (diff)
downloadcoreboot-e7a336ac29b1ef5aaa1b0aa4926ed75829b491b1.tar.xz
mips: add coherency argument to identity mapping
In order for a U-boot payload to work properly the soc_registers region (device registers) needs to be mapped as uncached. Therefore, add a coherency argument to the identity mapping funcion which will establish the type of mapping. Change-Id: I26fc546378acda4f4f8f4757fbc0adb03ac7db9f Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: https://review.coreboot.org/12769 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/mips/include/arch/cpu.h18
-rw-r--r--src/arch/mips/include/arch/mmu.h2
-rw-r--r--src/arch/mips/mmu.c8
3 files changed, 19 insertions, 9 deletions
diff --git a/src/arch/mips/include/arch/cpu.h b/src/arch/mips/include/arch/cpu.h
index 10fde8f3df..d43fd624a6 100644
--- a/src/arch/mips/include/arch/cpu.h
+++ b/src/arch/mips/include/arch/cpu.h
@@ -110,10 +110,20 @@ do { \
#define C0_ENTRYLO_PFN_SHIFT 6
-#define C0_ENTRYLO_WB (0x3 << 3) /* Cacheable, write-back, non-coherent */
-#define C0_ENTRYLO_D (0x1 << 2) /* Writeable */
-#define C0_ENTRYLO_V (0x1 << 1) /* Valid */
-#define C0_ENTRYLO_G (0x1 << 0) /* Global */
+
+#define C0_ENTRYLO_COHERENCY_MASK 0x00000038
+#define C0_ENTRYLO_COHERENCY_SHIFT 3
+/* Cacheable, write-back, non-coherent */
+#define C0_ENTRYLO_COHERENCY_WB (0x3 << C0_ENTRYLO_COHERENCY_SHIFT)
+/* Uncached, non-coherent */
+#define C0_ENTRYLO_COHERENCY_UC (0x2 << C0_ENTRYLO_COHERENCY_SHIFT)
+
+/* Writeable */
+#define C0_ENTRYLO_D (0x1 << 2)
+/* Valid */
+#define C0_ENTRYLO_V (0x1 << 1)
+/* Global */
+#define C0_ENTRYLO_G (0x1 << 0)
#define C0_PAGEMASK_SHIFT 13
#define C0_PAGEMASK_MASK 0xffff
diff --git a/src/arch/mips/include/arch/mmu.h b/src/arch/mips/include/arch/mmu.h
index ab17fec61e..8997e27f44 100644
--- a/src/arch/mips/include/arch/mmu.h
+++ b/src/arch/mips/include/arch/mmu.h
@@ -50,6 +50,6 @@ static inline uint32_t get_tlb_size(void)
return tlbsize;
}
-int identity_map(uint32_t start, size_t len);
+int identity_map(uint32_t start, size_t len, uint32_t coherency);
#endif /* __MIPS_ARCH_MMU_H */
diff --git a/src/arch/mips/mmu.c b/src/arch/mips/mmu.c
index 38f496deb3..b144fd3573 100644
--- a/src/arch/mips/mmu.c
+++ b/src/arch/mips/mmu.c
@@ -14,7 +14,6 @@
* GNU General Public License for more details.
*/
-#include <arch/cpu.h>
#include <arch/mmu.h>
#include <console/console.h>
#include <stddef.h>
@@ -70,22 +69,23 @@ static uint32_t pick_pagesize(uint32_t start, uint32_t len)
* Identity map the memory from [start,start+len] in the TLB using the
* largest suitable page size so as to conserve TLB entries.
*/
-int identity_map(uint32_t start, size_t len)
+int identity_map(uint32_t start, size_t len, uint32_t coherency)
{
uint32_t pgsize, pfn, entryhi, entrylo0, entrylo1;
+ coherency &= C0_ENTRYLO_COHERENCY_MASK;
while (len > 0) {
pgsize = pick_pagesize(start, len);
entryhi = start;
pfn = start >> 12;
- entrylo0 = (pfn << C0_ENTRYLO_PFN_SHIFT) | C0_ENTRYLO_WB |
+ entrylo0 = (pfn << C0_ENTRYLO_PFN_SHIFT) | coherency |
C0_ENTRYLO_D | C0_ENTRYLO_V | C0_ENTRYLO_G;
start += pgsize;
len -= MIN(len, pgsize);
if (len >= pgsize) {
pfn = start >> 12;
entrylo1 = (pfn << C0_ENTRYLO_PFN_SHIFT) |
- C0_ENTRYLO_WB | C0_ENTRYLO_D | C0_ENTRYLO_V |
+ coherency | C0_ENTRYLO_D | C0_ENTRYLO_V |
C0_ENTRYLO_G;
start += pgsize;
len -= MIN(len, pgsize);