summaryrefslogtreecommitdiff
path: root/src/arch
diff options
context:
space:
mode:
authorDavid Hendricks <dhendrix@chromium.org>2013-03-28 18:37:29 -0700
committerDavid Hendricks <dhendrix@chromium.org>2013-03-29 18:20:41 +0100
commit7762091fcb91710615f20229d43fc7fc7246ccdb (patch)
treecbd722b35798ce58e3f7e8c24f3c3bf87fcb73bd /src/arch
parentd4d6a407f74e241c0d00c2eeac2fb85e7f08f989 (diff)
downloadcoreboot-7762091fcb91710615f20229d43fc7fc7246ccdb.tar.xz
armv7: set cache level explicitly for dcache/unified cache case
This adds a missing CSSELR write in the case of a dcache or unified cache being invalidated by armv7_invalidate_caches(), ensuring that all levels of dcache/unified cache are invalidated as expected when the function is called. Change-Id: Ie90184bf8a8181afa3afe0786897455b30b7f022 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2947 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/armv7/lib/cache.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/arch/armv7/lib/cache.c b/src/arch/armv7/lib/cache.c
index da03a81fd8..d65e021623 100644
--- a/src/arch/armv7/lib/cache.c
+++ b/src/arch/armv7/lib/cache.c
@@ -310,6 +310,8 @@ void armv7_invalidate_caches(void)
case 0x2:
case 0x4:
/* dcache only or unified cache */
+ csselr = level << 1;
+ write_csselr(csselr);
dcache_invalidate_all();
break;
case 0x3: