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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-05 22:00:08 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-08 04:57:03 +0000
commit41d9b651491be2b6e0e144a2aaf3051f72863f13 (patch)
tree103d047d40fade96314b78a71d4142de4515ea7c /src/commonlib/lz4.c.inc
parentd157b3e1e0aa652bb067165659fb01badacb5020 (diff)
downloadcoreboot-41d9b651491be2b6e0e144a2aaf3051f72863f13.tar.xz
soc/intel: Fix SMRAM base MSR
Previous setting was correct but assumed SMI handler is always located at the beginning of TSEG. Break the assumption. Change-Id: I5da1a36fc95f76fa3225498bbac41b2dd4d1dfec Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34730 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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