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| author | Jonathan Neuschäfer <j.neuschaefer@gmx.net> | 2016-05-27 09:05:02 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-05-31 21:07:03 +0200 |
| commit | 4acb0e774220c0705a71689b6620c976297d417c (patch) | |
| tree | 1dfb1d5df4c4370739f3812088669293ddd80c39 /src/commonlib/lz4_wrapper.c | |
| parent | 0a54fb533d9b03ba4ad24bfc9180ee5803feef51 (diff) | |
| download | coreboot-4acb0e774220c0705a71689b6620c976297d417c.tar.xz | |
commonlib/lz4: Avoid unaligned memory access on RISC-V
From the User-Level ISA Specification v2.0:
"We do not mandate atomicity for misaligned accesses so simple
implementations can just use a machine trap and software handler to
handle misaligned accesses." (— http://riscv.org/specifications/)
Spike traps on unaligned accesses.
Change-Id: Ia57786916f4076cc08513f4e331c2deec9cfa785
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/14983
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/commonlib/lz4_wrapper.c')
| -rw-r--r-- | src/commonlib/lz4_wrapper.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/commonlib/lz4_wrapper.c b/src/commonlib/lz4_wrapper.c index 772f7918f4..93fa7e8e1d 100644 --- a/src/commonlib/lz4_wrapper.c +++ b/src/commonlib/lz4_wrapper.c @@ -63,6 +63,11 @@ static void LZ4_copy8(void *dst, const void *src) : [src]"r"(src), [dst]"r"(dst) : "memory" ); #endif +#elif defined(__riscv__) + /* RISC-V implementations may trap on any unaligned access. */ + int i; + for (i = 0; i < 8; i++) + ((uint8_t *)dst)[i] = ((uint8_t *)src)[i]; #else *(uint64_t *)dst = *(const uint64_t *)src; #endif |