arch/x86: introduce postcar stage/phase

Certain chipsets don't have a memory-mapped boot media
so their code execution for stages prior to DRAM initialization
is backed by SRAM or cache-as-ram. The postcar stage/phase
handles the cache-as-ram situation where in order to tear down
cache-as-ram one needs to be executing out of a backing
store that isn't transient. By current definition, cache-as-ram
is volatile and tearing it down leads to its contents disappearing.
Therefore provide a shim layer, postcar, that's loaded into
memory and executed which does 2 things:

1. Tears down cache-as-ram with a chipset helper function.
2. Loads and runs ramstage.

Because those 2 things are executed out of ram there's no issue
of the code's backing store while executing the code that
tears down cache-as-ram. The current implementation makes no
assumption regarding cacheability of the DRAM itself. If the
chipset code wishes to cache DRAM for loading of the postcar
stage/phase then it's also up to the chipset to handle any
coherency issues pertaining to cache-as-ram destruction.

Change-Id: Ia58efdadd0b48f20cfe7de2f49ab462306c3a19b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14140
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>

2 files changed, 6 insertions, 0 deletions

diff --git a/src/commonlib/Makefile.inc b/src/commonlib/Makefile.inc
index 2752922067..7c14f7cb8c 100644
--- a/src/commonlib/Makefile.inc
+++ b/src/commonlib/Makefile.inc
@@ -2,12 +2,14 @@ bootblock-y += mem_pool.c
 verstage-y += mem_pool.c
 romstage-y += mem_pool.c
 ramstage-y += mem_pool.c
+postcar-y += mem_pool.c
 
 bootblock-y += region.c
 verstage-y += region.c
 romstage-y += region.c
 ramstage-y += region.c
 smm-y += region.c
+postcar-y += region.c
 
 ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp1_1_relocate.c
 
@@ -16,8 +18,10 @@ verstage-y += cbfs.c
 romstage-y += cbfs.c
 ramstage-y += cbfs.c
 smm-y += cbfs.c
+postcar-y += cbfs.c
 
 bootblock-y += lz4_wrapper.c
 verstage-y += lz4_wrapper.c
 romstage-y += lz4_wrapper.c
 ramstage-y += lz4_wrapper.c
+postcar-y += lz4_wrapper.c
diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h
index 46c5d49e6b..adeb291728 100644
--- a/src/commonlib/include/commonlib/cbmem_id.h
+++ b/src/commonlib/include/commonlib/cbmem_id.h
@@ -20,6 +20,7 @@
 #define CBMEM_ID_ACPI		0x41435049
 #define CBMEM_ID_ACPI_GNVS	0x474e5653
 #define CBMEM_ID_ACPI_GNVS_PTR	0x474e5650
+#define CBMEM_ID_AFTER_CAR	0xc4787a93
 #define CBMEM_ID_AGESA_RUNTIME	0x41474553
 #define CBMEM_ID_AMDMCT_MEMINFO 0x494D454E
 #define CBMEM_ID_CAR_GLOBALS	0xcac4e6a3
@@ -71,6 +72,7 @@
 	{ CBMEM_ID_ACPI_GNVS,		"ACPI GNVS  " }, \
 	{ CBMEM_ID_ACPI_GNVS_PTR,	"GNVS PTR   " }, \
 	{ CBMEM_ID_AGESA_RUNTIME,	"AGESA RSVD " }, \
+	{ CBMEM_ID_AFTER_CAR,		"AFTER CAR"   }, \
 	{ CBMEM_ID_AMDMCT_MEMINFO,	"AMDMEM INFO" }, \
 	{ CBMEM_ID_CAR_GLOBALS,		"CAR GLOBALS" }, \
 	{ CBMEM_ID_CBTABLE,		"COREBOOT   " }, \