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authorAaron Durbin <adurbin@chromium.org>2016-02-10 10:56:06 -0600
committerMartin Roth <martinroth@google.com>2016-02-19 19:50:10 +0100
commite0969aec2573872b9f528e33edd2cf3fb84c5948 (patch)
tree25c7b837e62b40d6261ac9a58a190dc321e736a4 /src/commonlib
parentf6ada1c30755f3de22942996bfcf6490a9b7b6e4 (diff)
downloadcoreboot-e0969aec2573872b9f528e33edd2cf3fb84c5948.tar.xz
x86: add coreboot table entry for TSC info
The 8254 (Programmable Interrupt Timer) is becoming optional on x86 platforms -- either from saving power or not including it at all. To allow a payload to still use a TSC without doing calibration provide the TSC frequency information in the coreboot tables. That data is provided by code/logic already employed by platform. If tsc_freq_mhz() returns 0 or CONFIG_TSC_CONSTANT_RATE is not selected the coreboot table record isn't created. BUG=chrome-os-partner:50214 BRANCH=glados TEST=With all subsequent patches confirmed TSC is picked up in libpayload. Change-Id: Iaeadb85c2648587debcf55f4fa5351d0c287e971 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13670 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Diffstat (limited to 'src/commonlib')
-rw-r--r--src/commonlib/include/commonlib/coreboot_tables.h8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h
index 43adb09375..5c28791594 100644
--- a/src/commonlib/include/commonlib/coreboot_tables.h
+++ b/src/commonlib/include/commonlib/coreboot_tables.h
@@ -335,6 +335,14 @@ struct lb_cbmem_entry {
uint32_t id;
};
+#define LB_TAG_TSC_INFO 0x0032
+struct lb_tsc_info {
+ uint32_t tag;
+ uint32_t size;
+
+ uint32_t freq_khz;
+};
+
#define LB_TAG_SERIALNO 0x002a
#define MAX_SERIALNO_LENGTH 32