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| author | arch import user (historical) <svn@openbios.org> | 2005-07-06 17:17:25 +0000 |
|---|---|---|
| committer | arch import user (historical) <svn@openbios.org> | 2005-07-06 17:17:25 +0000 |
| commit | 6ca7636c8f52560e732cdd5b1c7829cda5aa2bde (patch) | |
| tree | cc45ae7c4dea6e2c5338f52b4314106bf07023be /src/config/Options.lb | |
| parent | b2ed53dd5669c2c3839633bd2b3b4af709a5b149 (diff) | |
| download | coreboot-6ca7636c8f52560e732cdd5b1c7829cda5aa2bde.tar.xz | |
Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-51
Creator: Yinghai Lu <yhlu@tyan.com>
cache_as_ram for AMD and some intel
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1967 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/config/Options.lb')
| -rw-r--r-- | src/config/Options.lb | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/config/Options.lb b/src/config/Options.lb index 370eba21c8..92104a0451 100644 --- a/src/config/Options.lb +++ b/src/config/Options.lb @@ -164,7 +164,7 @@ define CONFIG_CHIP_CONFIGURE end define CONFIG_USE_INIT default 0 - export used + export always comment "Use stage 1 initialization code" end @@ -270,7 +270,7 @@ define _RAMSTART end define USE_DCACHE_RAM default 0 - export used + export always comment "Use data cache as temporary RAM if possible" end define DCACHE_RAM_BASE |