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author | Stefan Reinauer <stepan@coresystems.de> | 2008-01-18 16:16:45 +0000 |
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committer | Stefan Reinauer <stepan@openbios.org> | 2008-01-18 16:16:45 +0000 |
commit | ca374d455cad29c546a2d310c331a4ae431c33f9 (patch) | |
tree | 63d7914ee3fb021750389ab5ef45b2f0d376d476 /src/config/coreboot_apc.ld | |
parent | 997afe6ca576dcc0117891294b5f51f29864f354 (diff) | |
download | coreboot-ca374d455cad29c546a2d310c331a4ae431c33f9.tar.xz |
rename linuxbios_* files, too.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3057 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/config/coreboot_apc.ld')
-rw-r--r-- | src/config/coreboot_apc.ld | 100 |
1 files changed, 100 insertions, 0 deletions
diff --git a/src/config/coreboot_apc.ld b/src/config/coreboot_apc.ld new file mode 100644 index 0000000000..9bca028ca1 --- /dev/null +++ b/src/config/coreboot_apc.ld @@ -0,0 +1,100 @@ +/* + * Memory map: + * + * DCACHE_RAM_BASE + * : data segment + * : bss segment + * : heap + * : stack + */ +/* + * Bootstrap code for the STPC Consumer + * Copyright (c) 1999 by Net Insight AB. All Rights Reserved. + */ + +/* + * Written by Johan Rydberg, based on work by Daniel Kahlin. + * Rewritten by Eric Biederman + * 2005.12 yhlu add coreboot_ram cross the vga font buffer handling + * 2006.05 yhlu tailed it to use it for AP code in cache + */ +/* + * We use ELF as output format. So that we can + * debug the code in some form. + */ +INCLUDE ldoptions + +ENTRY(_start) + +SECTIONS +{ + . = DCACHE_RAM_BASE; + /* + * First we place the code and read only data (typically const declared). + * This get placed in rom. + */ + .text : { + _text = .; + *(.text); + *(.text.*); + . = ALIGN(16); + _etext = .; + } + .rodata : { + _rodata = .; + . = ALIGN(4); + *(.rodata) + *(.rodata.*) + . = ALIGN(4); + _erodata = .; + } + /* + * After the code we place initialized data (typically initialized + * global variables). This gets copied into ram by startup code. + * __data_start and __data_end shows where in ram this should be placed, + * whereas __data_loadstart and __data_loadend shows where in rom to + * copy from. + */ + .data : { + _data = .; + *(.data) + _edata = .; + } + /* + * bss does not contain data, it is just a space that should be zero + * initialized on startup. (typically uninitialized global variables) + * crt0.S fills between _bss and _ebss with zeroes. + */ + _bss = .; + .bss . : { + *(.bss) + *(.sbss) + *(COMMON) + } + _ebss = .; + _end = .; + . = ALIGN(0x1000); + _stack = .; + .stack . : { + . = 0x4000; + } + _estack = .; + _heap = .; + .heap . : { + . = ALIGN(4); + } + _eheap = .; + /* The ram segment + * This is all address of the memory resident copy of coreboot. + */ + _ram_seg = _text; + _eram_seg = _eheap; + + _bogus = ASSERT( ( _eram_seg <= ((DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE))) , "coreboot_apc is too big"); + + /DISCARD/ : { + *(.comment) + *(.note) + *(.note.*) + } +} |