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authorYinghai Lu <yinghailu@gmail.com>2006-10-04 22:56:21 +0000
committerYinghai Lu <yinghailu@gmail.com>2006-10-04 22:56:21 +0000
commit5f9624d211a247c032a31b22c3b47158f7083c9e (patch)
treeebb62857cc949d561338d5b38b249523d700c714 /src/config
parent93a5a194c5863262ed9b9fabc4cd40efcf1fddd9 (diff)
downloadcoreboot-5f9624d211a247c032a31b22c3b47158f7083c9e.tar.xz
CONFIG_USE_PRINTK_IN_CAR and ht chain id for HTX support in
serengeti_cheeatah git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2439 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/config')
-rw-r--r--src/config/Options.lb25
1 files changed, 25 insertions, 0 deletions
diff --git a/src/config/Options.lb b/src/config/Options.lb
index 0d8aa765e3..aaaab35ac0 100644
--- a/src/config/Options.lb
+++ b/src/config/Options.lb
@@ -485,6 +485,13 @@ define TTYS0_LCS
export always
comment "Default flow control settings for the 8250 serial console uart"
end
+
+define CONFIG_USE_PRINTK_IN_CAR
+ default 0
+ export always
+ comment "use printk instead of print in CAR stage code"
+end
+
###############################################
# Mainboard options
@@ -744,6 +751,12 @@ end
# Options for memory mapped I/O
###############################################
+define PCI_IO_CFG_EXT
+ default 0
+ export always
+ comment "allow 4K register space via io CFG port"
+end
+
define PCIC0_CFGADDR
default none
format "0x%x"
@@ -907,6 +920,18 @@ define SB_HT_CHAIN_ON_BUS0
comment "this will make SB hypertransport chain sit on bus 0, if it is 1, will put sb ht chain on bus 0, if it is 2 will put other chain on 0x40, 0x80, 0xc0"
end
+define PCI_BUS_SEGN_BITS
+ default 0
+ export always
+ comment "It could be 0, 1, 2, 3 and 4 only"
+end
+
+define MMCONF_SUPPORT
+ default 0
+ export always
+ comment "enable mmconfig for pci conf"
+end
+
define HW_MEM_HOLE_SIZEK
default 0
export always