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| author | Julius Werner <jwerner@chromium.org> | 2019-03-05 16:53:33 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-03-08 08:33:24 +0000 |
| commit | cd49cce7b70e80b4acc49b56bb2bb94370b4d867 (patch) | |
| tree | 8e89136e2da7cf54453ba8c112eda94415b56242 /src/console/post.c | |
| parent | b3a8cc54dbaf833c590a56f912209a5632b71f49 (diff) | |
| download | coreboot-cd49cce7b70e80b4acc49b56bb2bb94370b4d867.tar.xz | |
coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/console/post.c')
| -rw-r--r-- | src/console/post.c | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/src/console/post.c b/src/console/post.c index 08bdaa18a9..236aa8cdaa 100644 --- a/src/console/post.c +++ b/src/console/post.c @@ -20,7 +20,7 @@ #include <device/device.h> #include <pc80/mc146818rtc.h> #include <smp/spinlock.h> -#if IS_ENABLED(CONFIG_POST_IO) +#if CONFIG(POST_IO) #include <arch/io.h> #endif @@ -40,7 +40,7 @@ void __weak mainboard_post(uint8_t value) #define mainboard_post(x) #endif -#if IS_ENABLED(CONFIG_CMOS_POST) +#if CONFIG(CMOS_POST) DECLARE_SPIN_LOCK(cmos_post_lock) @@ -48,7 +48,7 @@ DECLARE_SPIN_LOCK(cmos_post_lock) void cmos_post_log(void) { u8 code = 0; -#if IS_ENABLED(CONFIG_CMOS_POST_EXTRA) +#if CONFIG(CMOS_POST_EXTRA) u32 extra = 0; #endif @@ -58,13 +58,13 @@ void cmos_post_log(void) switch (cmos_read(CMOS_POST_BANK_OFFSET)) { case CMOS_POST_BANK_0_MAGIC: code = cmos_read(CMOS_POST_BANK_1_OFFSET); -#if IS_ENABLED(CONFIG_CMOS_POST_EXTRA) +#if CONFIG(CMOS_POST_EXTRA) extra = cmos_read32(CMOS_POST_BANK_1_EXTRA); #endif break; case CMOS_POST_BANK_1_MAGIC: code = cmos_read(CMOS_POST_BANK_0_OFFSET); -#if IS_ENABLED(CONFIG_CMOS_POST_EXTRA) +#if CONFIG(CMOS_POST_EXTRA) extra = cmos_read32(CMOS_POST_BANK_0_EXTRA); #endif break; @@ -82,9 +82,9 @@ void cmos_post_log(void) default: printk(BIOS_WARNING, "POST: Unexpected post code " "in previous boot: 0x%02x\n", code); -#if IS_ENABLED(CONFIG_ELOG) +#if CONFIG(ELOG) elog_add_event_word(ELOG_TYPE_LAST_POST_CODE, code); -#if IS_ENABLED(CONFIG_CMOS_POST_EXTRA) +#if CONFIG(CMOS_POST_EXTRA) if (extra) elog_add_event_dword(ELOG_TYPE_POST_EXTRA, extra); #endif @@ -92,7 +92,7 @@ void cmos_post_log(void) } } -#if IS_ENABLED(CONFIG_CMOS_POST_EXTRA) +#if CONFIG(CMOS_POST_EXTRA) void post_log_extra(u32 value) { spin_lock(&cmos_post_lock); @@ -146,14 +146,14 @@ static void cmos_post_code(u8 value) void post_code(uint8_t value) { -#if !IS_ENABLED(CONFIG_NO_POST) -#if IS_ENABLED(CONFIG_CONSOLE_POST) +#if !CONFIG(NO_POST) +#if CONFIG(CONSOLE_POST) printk(BIOS_EMERG, "POST: 0x%02x\n", value); #endif -#if IS_ENABLED(CONFIG_CMOS_POST) +#if CONFIG(CMOS_POST) cmos_post_code(value); #endif -#if IS_ENABLED(CONFIG_POST_IO) +#if CONFIG(POST_IO) outb(value, CONFIG_POST_IO_PORT); #endif #endif |