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authorStefan Reinauer <reinauer@chromium.org>2011-06-22 16:39:19 -0700
committerStefan Reinauer <stefan.reinauer@coreboot.org>2011-10-21 23:34:30 +0200
commitd1bc331855caab351a70676b5085787292a45fea (patch)
tree8d0ddcf777c4b7330e02495982f1f718f56d27fc /src/console/uart8250mem_console.c
parentb6010b8e70c25f93773bc464457f69fd4bb8a82e (diff)
downloadcoreboot-d1bc331855caab351a70676b5085787292a45fea.tar.xz
Extend coreboot table entry for serial ports
Add information about memory mapped/io mapped base addresses. and fix up libpayload to use the same structures Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: I5f7b5eda6063261b9acb7a46310172d4a5471dfb Reviewed-on: http://review.coreboot.org/261 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/console/uart8250mem_console.c')
-rw-r--r--src/console/uart8250mem_console.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/console/uart8250mem_console.c b/src/console/uart8250mem_console.c
index e622ad090c..923df99df1 100644
--- a/src/console/uart8250mem_console.c
+++ b/src/console/uart8250mem_console.c
@@ -28,6 +28,11 @@ static void uartmem_init(void)
uart_bar = uart_mem_init();
}
+u32 uartmem_getbaseaddr(void)
+{
+ return uart_bar;
+}
+
static void uartmem_tx_byte(unsigned char data)
{
if (!uart_bar)