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authorKyösti Mälkki <kyosti.malkki@gmail.com>2013-08-12 20:40:37 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2013-08-29 18:35:47 +0200
commit24100100181bd770ce0f1181a1770a0808790cde (patch)
treeed9b812999f747902f0294859f98b149848716f9 /src/console
parentf7381f8cd1cf4307dcccd5728fc11afce3610439 (diff)
downloadcoreboot-24100100181bd770ce0f1181a1770a0808790cde.tar.xz
usbdebug: Change debug port scanning
On AMD platforms, setting of USBDEBUG_DEFAULT_PORT=0 tries to scan all physical ports one after other in incrementing order. To avoid possible problems with other USB devices, one can select the port number here and bypass the scan. Intel platforms can communicate with usbdebug dongle on one physical port only, and this option makes no difference there. Change-Id: I45be6cc3aa91b74650eda2d444c9fcad39d58897 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3872 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
Diffstat (limited to 'src/console')
-rw-r--r--src/console/Kconfig25
1 files changed, 9 insertions, 16 deletions
diff --git a/src/console/Kconfig b/src/console/Kconfig
index c5e5f28449..b753be4023 100644
--- a/src/console/Kconfig
+++ b/src/console/Kconfig
@@ -146,9 +146,6 @@ config HAVE_USBDEBUG
def_bool n
config USBDEBUG
- def_bool n
-
-config USBDEBUG
bool "USB 2.0 EHCI debug dongle support"
default n
depends on HAVE_USBDEBUG
@@ -169,25 +166,21 @@ config USBDEBUG
If unsure, say N.
-# Note: This option doesn't make sense on Intel ICH / AMD SB600 southbridges
-# as those hardcode the physical USB port to be used as Debug Port to 1.
-# It cannot be changed by coreboot.
config USBDEBUG_DEFAULT_PORT
int "Default USB port to use as Debug Port"
- default 1
- depends on USBDEBUG && !SOUTHBRIDGE_INTEL_I82801GX && !SOUTHBRIDGE_AMD_SB600
+ default 0
+ depends on USBDEBUG
help
- This option selects which physical USB port coreboot will try to
- use as EHCI Debug Port first (valid values are: 1-15).
+ Selects which physical USB port usbdebug dongle is connected to.
+ Setting of 0 means to scan possible ports starting from 1.
- If coreboot doesn't detect an EHCI Debug Port dongle on this port,
- it will try all the other ports one after the other. This will take
- a few seconds of time though, and thus slow down the booting process.
+ Intel platforms have hardwired the debug port location and this
+ setting makes no difference there.
Hence, if you select the correct port here, you can speed up
- your boot time. Which USB port number (1-15) refers to which
- actual port on your mainboard (potentially also USB pin headers
- on your mainboard) is highly board-specific, and you'll likely
+ your boot time. Which USB port number refers to which actual
+ port on your mainboard (potentially also USB pin headers on
+ your mainboard) is highly board-specific, and you'll likely
have to find out by trial-and-error.
# TODO: Deps?