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authorRichard Spiegel <richard.spiegel@amd.corp-partner.google.com>2018-10-17 13:32:58 -0700
committerPatrick Georgi <pgeorgi@google.com>2018-10-18 12:49:43 +0000
commit6205221a7375f5b54ddee77b303915c593c35599 (patch)
tree4245b83da19cb639a1e3779d390a7d2b855d9fa6 /src/console
parente7e01116e72205113243e43b0ca1bed4c584c5b3 (diff)
downloadcoreboot-6205221a7375f5b54ddee77b303915c593c35599.tar.xz
soc/amd/stoneyridge: Replace double defined MISC MMIO reg. 0x40
Register 0x40 of miscellaneous MMIO is double defined, with different names, which makes it confusing. Eliminate MISC_MISC_CLK_CNTL_1, and move its only bit definition to MISC_CLK_CNTL1 (which is correctly placed among MMIO registers. BUG=b:117818431 TEST=Build grunt. Change-Id: I5ca5045498b8a81943282e0d6ecfbaecbd600d19 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/29175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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