summaryrefslogtreecommitdiff
path: root/src/console
diff options
context:
space:
mode:
authorSubrata Banik <subrata.banik@intel.com>2017-10-12 16:40:17 +0530
committerAaron Durbin <adurbin@chromium.org>2017-10-18 01:10:41 +0000
commitd2cadc39f3894612ca7714d5a4712bd3c09f42de (patch)
tree8876ec81c93a2ba890eb90aba7c96e06ac90aa39 /src/console
parent319e3b4cce73c441de485e4569498f95ab114211 (diff)
downloadcoreboot-d2cadc39f3894612ca7714d5a4712bd3c09f42de.tar.xz
soc/intel/cannonlake: Refactor memory layout calculation
This patch split entire memory layout calculation into two parts. 1. Generic memory layout 2. SoC specific reserve memory layout. usable memory start = TOLUD - Generic memory size - - soc specific reserve memory size. Change-Id: I56e253504a331c0663efb2b90eaa0567613aa508 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/console')
0 files changed, 0 insertions, 0 deletions