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authorArthur Heymans <arthur@aheymans.xyz>2018-12-22 16:02:25 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-05-15 17:56:56 +0000
commit5bb15f1a4d18bafaf51b17fd9ea6d861f2b9ebd2 (patch)
tree8bedf540cdcf995931cb65799c881ad9a697cf26 /src/console
parent56f768774a25320d738febf99c335abdb6eeafbe (diff)
downloadcoreboot-5bb15f1a4d18bafaf51b17fd9ea6d861f2b9ebd2.tar.xz
soc/intel/broadwell: Use C_ENVIRONMENT_BOOTBLOCK
This puts the cache-as-ram init in the bootblock. Before setting up cache as ram the microcode updates are applied. This removes the possibility for a normal/fallback setup although implementing this should be quite easy. Setting up LPC in the bootblock to output console on SuperIOs is not done in this patch, therefore BOOTBLOCK_CONSOLE is not yet selected. Change-Id: I44eb6d380dea5b82e3f009a46381a0f611bb7935 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30383 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
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