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authorJulius Werner <jwerner@chromium.org>2019-03-05 16:53:33 -0800
committerPatrick Georgi <pgeorgi@google.com>2019-03-08 08:33:24 +0000
commitcd49cce7b70e80b4acc49b56bb2bb94370b4d867 (patch)
tree8e89136e2da7cf54453ba8c112eda94415b56242 /src/console
parentb3a8cc54dbaf833c590a56f912209a5632b71f49 (diff)
downloadcoreboot-cd49cce7b70e80b4acc49b56bb2bb94370b4d867.tar.xz
coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/console')
-rw-r--r--src/console/console.c2
-rw-r--r--src/console/init.c6
-rw-r--r--src/console/post.c24
-rw-r--r--src/console/printk.c8
-rw-r--r--src/console/vtxprintf.c2
5 files changed, 21 insertions, 21 deletions
diff --git a/src/console/console.c b/src/console/console.c
index 1a6aec1285..50ee5c30e5 100644
--- a/src/console/console.c
+++ b/src/console/console.c
@@ -79,7 +79,7 @@ void console_write_line(uint8_t *buffer, size_t number_of_bytes)
}
-#if IS_ENABLED(CONFIG_GDB_STUB) && (ENV_ROMSTAGE || ENV_RAMSTAGE)
+#if CONFIG(GDB_STUB) && (ENV_ROMSTAGE || ENV_RAMSTAGE)
void gdb_hw_init(void)
{
__gdb_hw_init();
diff --git a/src/console/init.c b/src/console/init.c
index b7cc43aef2..43b499d816 100644
--- a/src/console/init.c
+++ b/src/console/init.c
@@ -73,7 +73,7 @@ int console_log_level(int msg_level)
if (msg_level <= log_level)
return CONSOLE_LOG_ALL;
- if (IS_ENABLED(CONFIG_CONSOLE_CBMEM) && (msg_level <= BIOS_DEBUG))
+ if (CONFIG(CONSOLE_CBMEM) && (msg_level <= BIOS_DEBUG))
return CONSOLE_LOG_FAST;
return 0;
@@ -83,10 +83,10 @@ asmlinkage void console_init(void)
{
init_log_level();
- if (IS_ENABLED(CONFIG_DEBUG_CONSOLE_INIT))
+ if (CONFIG(DEBUG_CONSOLE_INIT))
car_set_var(console_inited, 1);
- if (IS_ENABLED(CONFIG_EARLY_PCI_BRIDGE) && !ENV_SMM && !ENV_RAMSTAGE)
+ if (CONFIG(EARLY_PCI_BRIDGE) && !ENV_SMM && !ENV_RAMSTAGE)
pci_early_bridge_init();
console_hw_init();
diff --git a/src/console/post.c b/src/console/post.c
index 08bdaa18a9..236aa8cdaa 100644
--- a/src/console/post.c
+++ b/src/console/post.c
@@ -20,7 +20,7 @@
#include <device/device.h>
#include <pc80/mc146818rtc.h>
#include <smp/spinlock.h>
-#if IS_ENABLED(CONFIG_POST_IO)
+#if CONFIG(POST_IO)
#include <arch/io.h>
#endif
@@ -40,7 +40,7 @@ void __weak mainboard_post(uint8_t value)
#define mainboard_post(x)
#endif
-#if IS_ENABLED(CONFIG_CMOS_POST)
+#if CONFIG(CMOS_POST)
DECLARE_SPIN_LOCK(cmos_post_lock)
@@ -48,7 +48,7 @@ DECLARE_SPIN_LOCK(cmos_post_lock)
void cmos_post_log(void)
{
u8 code = 0;
-#if IS_ENABLED(CONFIG_CMOS_POST_EXTRA)
+#if CONFIG(CMOS_POST_EXTRA)
u32 extra = 0;
#endif
@@ -58,13 +58,13 @@ void cmos_post_log(void)
switch (cmos_read(CMOS_POST_BANK_OFFSET)) {
case CMOS_POST_BANK_0_MAGIC:
code = cmos_read(CMOS_POST_BANK_1_OFFSET);
-#if IS_ENABLED(CONFIG_CMOS_POST_EXTRA)
+#if CONFIG(CMOS_POST_EXTRA)
extra = cmos_read32(CMOS_POST_BANK_1_EXTRA);
#endif
break;
case CMOS_POST_BANK_1_MAGIC:
code = cmos_read(CMOS_POST_BANK_0_OFFSET);
-#if IS_ENABLED(CONFIG_CMOS_POST_EXTRA)
+#if CONFIG(CMOS_POST_EXTRA)
extra = cmos_read32(CMOS_POST_BANK_0_EXTRA);
#endif
break;
@@ -82,9 +82,9 @@ void cmos_post_log(void)
default:
printk(BIOS_WARNING, "POST: Unexpected post code "
"in previous boot: 0x%02x\n", code);
-#if IS_ENABLED(CONFIG_ELOG)
+#if CONFIG(ELOG)
elog_add_event_word(ELOG_TYPE_LAST_POST_CODE, code);
-#if IS_ENABLED(CONFIG_CMOS_POST_EXTRA)
+#if CONFIG(CMOS_POST_EXTRA)
if (extra)
elog_add_event_dword(ELOG_TYPE_POST_EXTRA, extra);
#endif
@@ -92,7 +92,7 @@ void cmos_post_log(void)
}
}
-#if IS_ENABLED(CONFIG_CMOS_POST_EXTRA)
+#if CONFIG(CMOS_POST_EXTRA)
void post_log_extra(u32 value)
{
spin_lock(&cmos_post_lock);
@@ -146,14 +146,14 @@ static void cmos_post_code(u8 value)
void post_code(uint8_t value)
{
-#if !IS_ENABLED(CONFIG_NO_POST)
-#if IS_ENABLED(CONFIG_CONSOLE_POST)
+#if !CONFIG(NO_POST)
+#if CONFIG(CONSOLE_POST)
printk(BIOS_EMERG, "POST: 0x%02x\n", value);
#endif
-#if IS_ENABLED(CONFIG_CMOS_POST)
+#if CONFIG(CMOS_POST)
cmos_post_code(value);
#endif
-#if IS_ENABLED(CONFIG_POST_IO)
+#if CONFIG(POST_IO)
outb(value, CONFIG_POST_IO_PORT);
#endif
#endif
diff --git a/src/console/printk.c b/src/console/printk.c
index 6050620dca..09522158a7 100644
--- a/src/console/printk.c
+++ b/src/console/printk.c
@@ -26,7 +26,7 @@
#include <stddef.h>
#include <trace.h>
-#if (!defined(__PRE_RAM__) && IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK)) || !IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK)
+#if (!defined(__PRE_RAM__) && CONFIG(HAVE_ROMSTAGE_CONSOLE_SPINLOCK)) || !CONFIG(HAVE_ROMSTAGE_CONSOLE_SPINLOCK)
DECLARE_SPIN_LOCK(console_lock)
#endif
@@ -49,7 +49,7 @@ int vprintk(int msg_level, const char *fmt, va_list args)
{
int i, log_this;
- if (IS_ENABLED(CONFIG_SQUELCH_EARLY_SMP) && ENV_CACHE_AS_RAM &&
+ if (CONFIG(SQUELCH_EARLY_SMP) && ENV_CACHE_AS_RAM &&
!boot_cpu())
return 0;
@@ -59,7 +59,7 @@ int vprintk(int msg_level, const char *fmt, va_list args)
DISABLE_TRACE;
#ifdef __PRE_RAM__
-#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK)
+#if CONFIG(HAVE_ROMSTAGE_CONSOLE_SPINLOCK)
spin_lock(romstage_console_lock());
#endif
#else
@@ -74,7 +74,7 @@ int vprintk(int msg_level, const char *fmt, va_list args)
}
#ifdef __PRE_RAM__
-#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK)
+#if CONFIG(HAVE_ROMSTAGE_CONSOLE_SPINLOCK)
spin_unlock(romstage_console_lock());
#endif
#else
diff --git a/src/console/vtxprintf.c b/src/console/vtxprintf.c
index b20c14e6a3..043a1dae37 100644
--- a/src/console/vtxprintf.c
+++ b/src/console/vtxprintf.c
@@ -20,7 +20,7 @@
#define call_tx(x) tx_byte(x, data)
-#if !IS_ENABLED(CONFIG_ARCH_MIPS)
+#if !CONFIG(ARCH_MIPS)
#define SUPPORT_64BIT_INTS
#endif