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| author | Felix Held <felix.held@amd.corp-partner.google.com> | 2020-04-04 01:47:37 +0200 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2020-04-29 05:38:00 +0000 |
| commit | ca928c6768ba143f619a99cca44f9f8153511270 (patch) | |
| tree | 5a005a84adce4b0771a6fbe76de257c25604c55f /src/cpu/Kconfig | |
| parent | 3ae3ff28286f1e752f01ccf9480414ff1d82615f (diff) | |
| download | coreboot-ca928c6768ba143f619a99cca44f9f8153511270.tar.xz | |
arch/x86: Implement RESET_VECTOR_IN_RAM
Add support for devices with the reset vector pointing into DRAM. This
is a specific implementation that assumes a paradigm of AMD Family 17h
(a.k.a. "Zen"). Until the first ljmpl for protected mode, the core's
state appears to software like other designs, and then the actual
physical addressing becomes recognizable.
These systems cannot implement cache-as-RAM as in more traditional
x86 products. Therefore instead of reusing CAR names and variables,
a substitute called "earlyram" is introduced. This change makes
adjustments to CAR-aware files accordingly.
Enable NO_XIP_EARLY_STAGES. The first stage is already in DRAM, and
running subsequent stages as XIP in the boot device would reduce
performance.
Finally, add a new early_ram.ld linker file. Because all stages run in
DRAM, they can be linked with their .data and .bss as normal, i.e. they
don't need to rely on storage available only at a fixed location like
CAR systems. The primary purpose of the early_ram.ld is to provide
consistent locations for PRERAM_CBMEM_CONSOLE, TIMESTAMP regions, etc.
across stages until cbmem is brought online.
BUG=b:147042464
TEST=Build for trembyle, and boot to ramstage.
$ objdump -h cbfs/fallback/bootblock.debug
Idx ,Name ,Size ,VMA ,LMA ,File off Algn
0 ,.text ,000074d0 ,08076000 ,08076000 ,00001000 2**12
1 ,.data ,00000038 ,0807d4d0 ,0807d4d0 ,000084d0 2**2
2 ,.bss ,00000048 ,0807d508 ,0807d508 ,00008508 2**2
3 ,.stack ,00000800 ,0807daf0 ,0807daf0 ,00000000 2**0
4 ,.persistent ,00001cfa ,0807e2f0 ,0807e2f0 ,00000000 2**0
5 ,.reset ,00000010 ,0807fff0 ,0807fff0 ,0000aff0 2**0
6 ,.debug_info ,0002659c ,00000000 ,00000000 ,0000b000 2**0
7 ,.debug_abbrev ,000074a2 ,00000000 ,00000000 ,0003159c 2**0
8 ,.debug_aranges,00000dd0 ,00000000 ,00000000 ,00038a40 2**3
9 ,.debug_line ,0000ad65 ,00000000 ,00000000 ,00039810 2**0
10 ,.debug_str ,00009655 ,00000000 ,00000000 ,00044575 2**0
11 ,.debug_loc ,0000b7ce ,00000000 ,00000000 ,0004dbca 2**0
12 ,.debug_ranges ,000029c0 ,00000000 ,00000000 ,00059398 2**3
Change-Id: I9c084ff6fdcf7e9154436f038705e8679daea780
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35035
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/Kconfig')
| -rw-r--r-- | src/cpu/Kconfig | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index c1b84f9d44..933e50f227 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -15,6 +15,10 @@ config DCACHE_RAM_SIZE config DCACHE_BSP_STACK_SIZE hex +config EARLYRAM_BSP_STACK_SIZE + depends on RESET_VECTOR_IN_RAM + hex + config SMP bool default y if MAX_CPUS != 1 |