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| author | David Hendricks <dhendrix@chromium.org> | 2012-12-31 17:28:43 -0800 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-01-04 01:36:27 +0100 |
| commit | 6a503b6a0f08bf4236c4c37d75c67182a7af4b02 (patch) | |
| tree | 79aaedcb8283cb543fe47072c839de6f22354d7f /src/cpu/Kconfig | |
| parent | 10c90d31264b5698320a1ac2666823532d110258 (diff) | |
| download | coreboot-6a503b6a0f08bf4236c4c37d75c67182a7af4b02.tar.xz | |
make early serial console support more generic
This patch makes pre-RAM serial init more generic, particularly for
platforms which do not necessarily need cache-as-RAM in order to use
the serial console and do not have a standard 8250 serial port.
This adds a Kconfig variable to set romstage-* for very early serial
console init. The current method assumes that cache-as-RAM should
enable this, so to maintain compatibility selecting CACHE_AS_RAM will
also select EARLY_SERIAL_CONSOLE.
The UART code structure needs some rework, but the use of ROMCC,
romstage, and then ramstage makes things complex.
uart.h now includes all .h files for all uarts. All 2 of them.
This is actually a simplifying change.
Change-Id: I089e7af633c227baf3c06c685f005e9d0e4b38ce
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2086
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/cpu/Kconfig')
| -rw-r--r-- | src/cpu/Kconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index 383ba796a2..ddc46cf393 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -16,6 +16,7 @@ source src/cpu/x86/Kconfig config CACHE_AS_RAM bool + select EARLY_SERIAL_CONSOLE default !ROMCC config DCACHE_RAM_BASE |