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| author | Marc Jones <marc.jones@se-eng.com> | 2013-10-29 17:46:54 -0600 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2013-12-04 18:45:42 +0100 |
| commit | bdafcfa55509d0cf2cbbb686411f569d56d3916c (patch) | |
| tree | 8a46755738c18acbbfb2678cc6ff76439543bb30 /src/cpu/Kconfig | |
| parent | 54b8e7a0bba7787eca737506cb5d85bf408344d2 (diff) | |
| download | coreboot-bdafcfa55509d0cf2cbbb686411f569d56d3916c.tar.xz | |
Add the Intel FSP 206ax CPU core support
Add support for 206ax using the Intel FSP.
The FSP is different enough to warrant its own source files
for now. It has different CAR code, micorcode, and FSP inclusion.
It may be possible to combine this code with the mrc based
solution used by the chromebooks in the future.
Change-Id: I5105631af34e9c3a804ace908c4205f073abb9b4
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/4016
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/cpu/Kconfig')
| -rw-r--r-- | src/cpu/Kconfig | 39 |
1 files changed, 37 insertions, 2 deletions
diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index e48fe877e0..46b6f1c765 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -77,10 +77,32 @@ config CPU_MICROCODE_IN_CBFS bool default n +# The following options (BOARD_MICROCODE_CBFS_*) make it possible for the +# microcode configuration to be selected in the board-level Kconfig. If +# you want your platform's microcode to be generated during the build, +# add "select BOARD_MICROCODE_CBFS_GENERATE" to your mainboard's Kconfig. +# If you want to use an external microcode file, add "select +# BOARD_MICROCODE_CBFS_EXTERNAL" instead. If neither of these statements +# exists in your mainboard's configuration file (or if you include a +# "select BOARD_MICROCODE_CBFS_NONE" statement), then the ROM image will +# be built without any microcode. +config BOARD_MICROCODE_CBFS_NONE + bool + default y + +config BOARD_MICROCODE_CBFS_GENERATE + bool + default n + +config BOARD_MICROCODE_CBFS_EXTERNAL + bool + default n + choice prompt "Include CPU microcode in CBFS" if ARCH_X86 - default CPU_MICROCODE_CBFS_GENERATE if CPU_MICROCODE_IN_CBFS - default CPU_MICROCODE_CBFS_NONE if !CPU_MICROCODE_IN_CBFS + default CPU_MICROCODE_CBFS_GENERATE if CPU_MICROCODE_IN_CBFS && BOARD_MICROCODE_CBFS_GENERATE + default CPU_MICROCODE_CBFS_EXTERNAL if CPU_MICROCODE_IN_CBFS && BOARD_MICROCODE_CBFS_EXTERNAL + default CPU_MICROCODE_CBFS_NONE config CPU_MICROCODE_CBFS_GENERATE bool "Generate from tree" @@ -158,3 +180,16 @@ config CPU_MICROCODE_FILE default "cpu_microcode.bin" help The path and filename of the file containing the CPU microcode. + +config CPU_MICROCODE_CBFS_LOC + hex "Microcode address in CBFS" + depends on CPU_MICROCODE_IN_CBFS + default 0 + +config CPU_MICROCODE_CBFS_LEN + hex "Microcode length in CBFS" + depends on CPU_MICROCODE_IN_CBFS + default 0xC000 + help + The microcode needs a specific length to get correctly + detected and loaded by all CPUs. |