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| author | Xavi Drudis Ferran <xdrudis@tinet.cat> | 2011-02-28 00:31:24 +0000 |
|---|---|---|
| committer | Marc Jones <marc.jones@amd.com> | 2011-02-28 00:31:24 +0000 |
| commit | 6fcc961fe846aca897480bb637142d50914a4ea7 (patch) | |
| tree | a1f337d1cdb2e98bbd0b30a62b5624d342c621d8 /src/cpu/Makefile.inc | |
| parent | 1f93fea160fff042f7d5467c56eaf2fc0286995f (diff) | |
| download | coreboot-6fcc961fe846aca897480bb637142d50914a4ea7.tar.xz | |
Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.
Configuration of F3x[84:80] was hardcoded for rev B.
I change that for some code that checks for revision
and configures according to BKDG. Unfinished but
hopefully better than it was.
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6398 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/Makefile.inc')
0 files changed, 0 insertions, 0 deletions