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authorJulius Werner <jwerner@chromium.org>2015-02-19 14:08:04 -0800
committerPatrick Georgi <pgeorgi@google.com>2015-04-21 08:21:15 +0200
commitd21a329866a1299b180f8b14b6c73bee3d754e57 (patch)
tree499483d184466d1aa71af356d46b6ab8c73b3082 /src/cpu/allwinner/a10/timer.c
parent24f94765311429d937befb4bebe1632eb683fd2c (diff)
downloadcoreboot-d21a329866a1299b180f8b14b6c73bee3d754e57.tar.xz
arm(64): Replace write32() and friends with writel()
This patch is a raw application of the following spatch to the directories src/arch/arm(64)?, src/mainboard/<arm(64)-board>, src/soc/<arm(64)-soc> and src/drivers/gic: @@ expression A, V; @@ - write32(V, A) + writel(V, A) @@ expression A, V; @@ - write16(V, A) + writew(V, A) @@ expression A, V; @@ - write8(V, A) + writeb(V, A) This replaces all uses of write{32,16,8}() with write{l,w,b}() which is currently equivalent and much more common. This is a preparatory step that will allow us to easier flip them all at once to the new write32(a,v) model. BRANCH=none BUG=chromium:451388 TEST=Compiled Cosmos, Daisy, Blaze, Pit, Ryu, Storm and Pinky. Change-Id: I16016cd77780e7cadbabe7d8aa7ab465b95b8f09 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 93f0ada19b429b4e30d67335b4e61d0f43597b24 Original-Change-Id: I1ac01c67efef4656607663253ed298ff4d0ef89d Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/254862 Reviewed-on: http://review.coreboot.org/9834 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/cpu/allwinner/a10/timer.c')
-rw-r--r--src/cpu/allwinner/a10/timer.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/cpu/allwinner/a10/timer.c b/src/cpu/allwinner/a10/timer.c
index 7d5d1419c3..2ff88f528d 100644
--- a/src/cpu/allwinner/a10/timer.c
+++ b/src/cpu/allwinner/a10/timer.c
@@ -24,13 +24,13 @@ void init_timer(void)
{
u32 reg32;
/* Load the timer rollover value */
- write32(0xffffffff, &tmr0->interval);
+ writel(0xffffffff, &tmr0->interval);
/* Configure the timer to run from 24MHz oscillator, no prescaler */
reg32 = TIMER_CTRL_PRESC_DIV_EXP(0);
reg32 |= TIMER_CTRL_CLK_SRC_OSC24M;
reg32 |= TIMER_CTRL_RELOAD;
reg32 |= TIMER_CTRL_TMR_EN;
- write32(reg32, &tmr0->ctrl);
+ writel(reg32, &tmr0->ctrl);
}
void udelay(unsigned usec)
@@ -61,6 +61,6 @@ void udelay(unsigned usec)
*/
u8 a1x_get_cpu_chip_revision(void)
{
- write32(0, &timer_module->cpu_cfg);
+ writel(0, &timer_module->cpu_cfg);
return (read32(&timer_module->cpu_cfg) >> 6) & 0x3;
}