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authorElyes HAOUAS <ehaouas@noos.fr>2016-08-21 10:12:15 +0200
committerMartin Roth <martinroth@google.com>2016-08-23 15:43:58 +0200
commitd6e96864c9245b82222dada6fea2b89ccb7fecfd (patch)
tree9d850d9cfc15d19792da114d426009cc6fb208fa /src/cpu/allwinner
parent38424987c6d19015e4572d5371a0f9f621fc46fa (diff)
downloadcoreboot-d6e96864c9245b82222dada6fea2b89ccb7fecfd.tar.xz
src/cpu: Capitalize CPU, APIC and IOAPIC typo fix
Change-Id: I82e0736dc6b44cfcc57cdfdc786c85c4b6882260 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16276 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker
Diffstat (limited to 'src/cpu/allwinner')
-rw-r--r--src/cpu/allwinner/a10/clock.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/allwinner/a10/clock.h b/src/cpu/allwinner/a10/clock.h
index d1729a3e68..a723ecc0b6 100644
--- a/src/cpu/allwinner/a10/clock.h
+++ b/src/cpu/allwinner/a10/clock.h
@@ -212,7 +212,7 @@ struct a10_ccm {
u8 res3[0xc];
u32 pll_lock_dbg; /* 0x4c pll lock time debug */
u32 osc24m_cfg; /* 0x50 osc24m control */
- u32 cpu_ahb_apb0_cfg; /* 0x54 cpu,ahb and apb0 divide ratio */
+ u32 cpu_ahb_apb0_cfg; /* 0x54 CPU, ahb and apb0 divide ratio */
u32 apb1_clk_div_cfg; /* 0x58 apb1 clock dividor */
u32 axi_gate; /* 0x5c axi module clock gating */
u32 ahb_gate0; /* 0x60 ahb module clock gating 0 */