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authorEdward O'Callaghan <eocallaghan@alterapraxis.com>2014-07-08 01:53:24 +1000
committerEdward O'Callaghan <eocallaghan@alterapraxis.com>2014-07-11 08:39:07 +0200
commit7116ac803736345cc7c7b73ac435efa50c4cd2b0 (patch)
tree64b7190ef4e61ba2e17a88c50e92c076c3aa2d19 /src/cpu/allwinner
parentc805e62f9dd5e1b11906101845abd36b049e7dc3 (diff)
downloadcoreboot-7116ac803736345cc7c7b73ac435efa50c4cd2b0.tar.xz
src: Make use of 'CEIL_DIV(a, b)' macro across tree
The objective here is to tighten coreboot up a bit by not repeating common helpers. This makes the code base more consistent and unified/tight. Change-Id: Ia163eae68b4a84a00ed118125e70308fab1cea0c Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6215 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/cpu/allwinner')
-rw-r--r--src/cpu/allwinner/a10/clock.c9
1 files changed, 2 insertions, 7 deletions
diff --git a/src/cpu/allwinner/a10/clock.c b/src/cpu/allwinner/a10/clock.c
index 945dfd767b..f189aeae02 100644
--- a/src/cpu/allwinner/a10/clock.c
+++ b/src/cpu/allwinner/a10/clock.c
@@ -159,11 +159,6 @@ static const struct {
{ PLL1_CFG(20, 4, 1, 0), 1944 },
};
-static inline u32 div_ceil(u32 a, u32 b)
-{
- return (a + b - 1) / b;
-}
-
static void cpu_clk_src_switch(u32 clksel_bits)
{
u32 reg32;
@@ -241,8 +236,8 @@ void a1x_set_cpu_clock(u16 cpu_clk_mhz)
* will always be in spec, as long as AHB is in spec, although the max
* AHB0 clock we can get is 125 MHz
*/
- axi = div_ceil(actual_mhz, 450); /* Max 450 MHz */
- ahb = div_ceil(actual_mhz/axi, 250); /* Max 250 MHz */
+ axi = CEIL_DIV(actual_mhz, 450); /* Max 450 MHz */
+ ahb = CEIL_DIV(actual_mhz/axi, 250); /* Max 250 MHz */
apb0 = 2; /* Max 150 MHz */
ahb_exp = log2_ceil(ahb);