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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-11-22 12:00:52 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-03-28 01:57:37 +0200 |
| commit | 77d3c4b69003a9b5d864190be334f7239623789c (patch) | |
| tree | aef99fe0e6956153509a901b2d4ae363c5e63654 /src/cpu/amd/agesa/Makefile.inc | |
| parent | 967d94d62630f46a2fab808754e7a2702658f3f0 (diff) | |
| download | coreboot-77d3c4b69003a9b5d864190be334f7239623789c.tar.xz | |
AGESA: Fork for new cache-as-ram init code
To gradually consolidate and improve AGESA board romstages,
fork the original CAR setup code as a separate file. It becomes
too messy with preprocessor to attempt make changes within the
same file, and at end of patchset original becomes obsolete.
Change-Id: I256b675b1ab9e13c2bcc956e0d67c6c03e91f2ed
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18620
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/cpu/amd/agesa/Makefile.inc')
| -rw-r--r-- | src/cpu/amd/agesa/Makefile.inc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc index 60bae120bc..9853d63c5f 100644 --- a/src/cpu/amd/agesa/Makefile.inc +++ b/src/cpu/amd/agesa/Makefile.inc @@ -23,7 +23,11 @@ subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) += family16kb romstage-y += s3_resume.c ramstage-y += s3_mtrr.c +ifeq ($(CONFIG_AGESA_LEGACY), y) +cpu_incs-y += $(src)/cpu/amd/agesa/cache_as_ram_legacy.inc +else cpu_incs-y += $(src)/cpu/amd/agesa/cache_as_ram.inc +endif romstage-y += heapmanager.c ramstage-y += heapmanager.c |