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authorefdesign98 <efdesign98@gmail.com>2011-07-13 17:16:13 -0700
committerPatrick Georgi <patrick@georgi-clan.de>2011-07-18 21:59:14 +0200
commit4b508341bcf11687be98d20f8178b5cc542a0842 (patch)
treed2ccbff67002346232d4e9689e1f597054443408 /src/cpu/amd/agesa/family12
parentb58640c5ef26ea49db8d94fa4962de3354bd2af2 (diff)
downloadcoreboot-4b508341bcf11687be98d20f8178b5cc542a0842.tar.xz
Add AMD Family 10 support to cpu folder
This change adds the AMD Family 10 cpu support to the cpu folder. It also updates the makefiles of the Families 12 and 14 to take advantage of a pair of shared files that are moved to the cpu/agesa folder. Change-Id: Ibd3a50ea7a3028bd6a2d2583f021506b73e2fce2 Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/97 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/cpu/amd/agesa/family12')
-rwxr-xr-xsrc/cpu/amd/agesa/family12/Makefile.inc4
-rwxr-xr-xsrc/cpu/amd/agesa/family12/apic_timer.c58
-rwxr-xr-xsrc/cpu/amd/agesa/family12/cache_as_ram.inc98
3 files changed, 0 insertions, 160 deletions
diff --git a/src/cpu/amd/agesa/family12/Makefile.inc b/src/cpu/amd/agesa/family12/Makefile.inc
index 4e69355bbb..5aa41276e1 100755
--- a/src/cpu/amd/agesa/family12/Makefile.inc
+++ b/src/cpu/amd/agesa/family12/Makefile.inc
@@ -320,7 +320,3 @@ subdirs-y += ../../../x86/cache
subdirs-y += ../../../x86/mtrr
subdirs-y += ../../../x86/pae
subdirs-y += ../../../x86/smm
-
-ramstage-y += apic_timer.c
-
-cpu_incs += $(src)/cpu/amd/agesa/family12/cache_as_ram.inc
diff --git a/src/cpu/amd/agesa/family12/apic_timer.c b/src/cpu/amd/agesa/family12/apic_timer.c
deleted file mode 100755
index 26d3f88e49..0000000000
--- a/src/cpu/amd/agesa/family12/apic_timer.c
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- *****************************************************************************
- *
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- * ***************************************************************************
- *
- */
-
-#include <stdint.h>
-#include <delay.h>
-#include <cpu/x86/msr.h>
-#include <cpu/x86/lapic.h>
-
-/* NOTE: We use the APIC TIMER register is to hold flags for AP init during
- * pre-memory init (__PRE_RAM__). Don't use init_timer() and udelay is
- * redirected to udelay_tsc().
- */
-
-
-void init_timer(void)
-{
- /* Set the apic timer to no interrupts and periodic mode */
- lapic_write(LAPIC_LVTT, (1 << 17)|(1<< 16)|(0 << 12)|(0 << 0));
-
- /* Set the divider to 1, no divider */
- lapic_write(LAPIC_TDCR, LAPIC_TDR_DIV_1);
-
- /* Set the initial counter to 0xffffffff */
- lapic_write(LAPIC_TMICT, 0xffffffff);
-}
-
-
-void udelay(u32 usecs)
-{
- u32 start, value, ticks;
- /* Calculate the number of ticks to run, our FSB runs a 200Mhz */
- ticks = usecs * 200;
- start = lapic_read(LAPIC_TMCCT);
- do {
- value = lapic_read(LAPIC_TMCCT);
- } while((start - value) < ticks);
-
-}
diff --git a/src/cpu/amd/agesa/family12/cache_as_ram.inc b/src/cpu/amd/agesa/family12/cache_as_ram.inc
deleted file mode 100755
index 98da3cbffb..0000000000
--- a/src/cpu/amd/agesa/family12/cache_as_ram.inc
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/******************************************************************************
- * AMD Generic Encapsulated Software Architecture
- *
- * $Workfile:: cache_as_ram.inc
- *
- * Description: cache_as_ram.inc - AGESA Module Entry Point for GCC complier
- *
- ******************************************************************************
- */
-
-#include "gcccar.inc"
-
-/*
- * XMM map:
- * xmm0: BIST
- * xmm1: backup ebx -- cpu_init_detected
- */
-
-.code32
-.globl cache_as_ram_setup, disable_cache_as_ram, cache_as_ram_setup_out
-
-cache_as_ram_setup:
-
- post_code(0xa0)
-
- /* enable SSE2 128bit instructions */
- /* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */
-
- movl %cr4, %eax
- orl $(3<<9), %eax
- movl %eax, %cr4
-
- /* Get the cpu_init_detected */
- mov $1, %eax
- cpuid
- shr $24, %ebx
-
- /* Save the BIST result */
- cvtsi2sd %ebp, %xmm0
-
- /* for normal part %ebx already contain cpu_init_detected from fallback call */
-
- /* Save the cpu_init_detected */
- cvtsi2sd %ebx, %xmm1
-
- post_code(0xa1)
- AMD_ENABLE_STACK
-
- post_code(0xa1)
-
- /* Restore the BIST result */
- cvtsd2si %xmm0, %edx
-
- /* Restore the cpu_init_detected */
- cvtsd2si %xmm1, %ebx
-
- pushl %ebx /* init detected */
- pushl %edx /* bist */
- call cache_as_ram_main
-
- /* Should never see this postcode */
- post_code(0xaf)
-stop:
- jmp stop
-
-disable_cache_as_ram:
- /* Save return stack */
- cvtsi2sd %esp, %xmm0
-
- AMD_DISABLE_STACK
-
- /* Restore the return stack */
- cvtsd2si %xmm0, %esp
-
- ret
-
-cache_as_ram_setup_out:
-
-