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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-10-23 17:10:27 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-10-30 20:18:53 +0000 |
| commit | 8a643703b87630b4346e52cac3d3acdc95ac1c70 (patch) | |
| tree | e7ec84129a9c02940b8fd8bbd778601b15c0956a /src/cpu/amd/agesa/family15tn | |
| parent | 50f2e4ccec9df213e012c7ecddb0a9c644526c8d (diff) | |
| download | coreboot-8a643703b87630b4346e52cac3d3acdc95ac1c70.tar.xz | |
{cpu,drivers,nb,sb}/amd: Replace {MSR,MTRR} addresses with macros
Change-Id: I7e8de35dcdad52bb311b34bfa9b272d17ed3186b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29243
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/amd/agesa/family15tn')
| -rw-r--r-- | src/cpu/amd/agesa/family15tn/fixme.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/cpu/amd/agesa/family15tn/fixme.c b/src/cpu/amd/agesa/family15tn/fixme.c index 7e493f9dda..a0ae193bcf 100644 --- a/src/cpu/amd/agesa/family15tn/fixme.c +++ b/src/cpu/amd/agesa/family15tn/fixme.c @@ -15,6 +15,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/msr.h> +#include <cpu/amd/mtrr.h> #include <northbridge/amd/agesa/agesa_helper.h> #include <AGESA.h> #include "amdlib.h" @@ -47,7 +48,7 @@ void amd_initcpuio(void) PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C); PciData = 0x00FECF00; /* last address before non-posted range */ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader); + LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader); MsrReg = (MsrReg >> 8) | 3; PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88); PciData = (UINT32)MsrReg; |