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authorElyes HAOUAS <ehaouas@noos.fr>2018-10-17 20:18:17 +0200
committerPatrick Georgi <pgeorgi@google.com>2018-10-19 09:20:22 +0000
commitd50cf23e43bb2e54210b2e719bbf53002814926b (patch)
treeae17611aeca5d7f941cac99d48a23ff9d92dee15 /src/cpu/amd/agesa/family15tn
parent253cd5a7e6e2a651c2b0b85ebb6e9103567cae31 (diff)
downloadcoreboot-d50cf23e43bb2e54210b2e719bbf53002814926b.tar.xz
{cpu,drivers}/amd: Replace MTRR addresses with macros
Change-Id: I315c0b70c552c5dd7f640b18b913350bb88be81b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29173 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/amd/agesa/family15tn')
-rw-r--r--src/cpu/amd/agesa/family15tn/fixme.c4
-rw-r--r--src/cpu/amd/agesa/family15tn/model_15_init.c10
2 files changed, 7 insertions, 7 deletions
diff --git a/src/cpu/amd/agesa/family15tn/fixme.c b/src/cpu/amd/agesa/family15tn/fixme.c
index 847f75393f..7e493f9dda 100644
--- a/src/cpu/amd/agesa/family15tn/fixme.c
+++ b/src/cpu/amd/agesa/family15tn/fixme.c
@@ -76,7 +76,7 @@ void amd_initmmio(void)
/* Set ROM cache onto WP to decrease post time */
MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
- LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
+ LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader);
MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
- LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
+ LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader);
}
diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c
index d188bcc84b..847eb6a52b 100644
--- a/src/cpu/amd/agesa/family15tn/model_15_init.c
+++ b/src/cpu/amd/agesa/family15tn/model_15_init.c
@@ -54,12 +54,12 @@ static void model_15_init(struct device *dev)
// BSP: make a0000-bffff UC, c0000-fffff WB, same as OntarioApMtrrSettingsList for APs
msr.lo = msr.hi = 0;
- wrmsr (0x259, msr);
+ wrmsr(MTRR_FIX_16K_A0000, msr);
msr.lo = msr.hi = 0x1e1e1e1e;
- wrmsr(0x250, msr);
- wrmsr(0x258, msr);
- for (msrno = 0x268; msrno <= 0x26f; msrno++)
- wrmsr (msrno, msr);
+ wrmsr(MTRR_FIX_64K_00000, msr);
+ wrmsr(MTRR_FIX_16K_80000, msr);
+ for (msrno = MTRR_FIX_4K_C0000; msrno <= MTRR_FIX_4K_F8000; msrno++)
+ wrmsr(msrno, msr);
msr = rdmsr(SYSCFG_MSR);
msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;