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authorKyösti Mälkki <kyosti.malkki@gmail.com>2016-11-20 17:31:58 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2016-12-01 05:49:53 +0100
commitb995f436b355ec357788d3a8c11c70bf5ec437df (patch)
treeab462648d08c0b392992c643e79470709ab282b8 /src/cpu/amd/agesa/family15tn
parent59e03342076ea79cb7c0ed2fdbd199947c8c5212 (diff)
downloadcoreboot-b995f436b355ec357788d3a8c11c70bf5ec437df.tar.xz
AGESA: Disable PCI_CFG_EXT_IO
We don't need to do explicit pci_io_read/write operations, as we can use MMCONF everywhere. AGESA code still enables extended cf8/cfc should it be required by payload or OS. Change-Id: I278e5e26eb9a247f67927cbc67e04f081ca50f7b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17535 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/cpu/amd/agesa/family15tn')
-rw-r--r--src/cpu/amd/agesa/family15tn/Kconfig1
-rw-r--r--src/cpu/amd/agesa/family15tn/fixme.c7
2 files changed, 0 insertions, 8 deletions
diff --git a/src/cpu/amd/agesa/family15tn/Kconfig b/src/cpu/amd/agesa/family15tn/Kconfig
index 3f8a3f07c2..1f41560a4d 100644
--- a/src/cpu/amd/agesa/family15tn/Kconfig
+++ b/src/cpu/amd/agesa/family15tn/Kconfig
@@ -15,7 +15,6 @@
config CPU_AMD_AGESA_FAMILY15_TN
bool
- select PCI_IO_CFG_EXT
select MMCONF_SUPPORT_DEFAULT
select X86_AMD_FIXED_MTRRS
diff --git a/src/cpu/amd/agesa/family15tn/fixme.c b/src/cpu/amd/agesa/family15tn/fixme.c
index b7d890392e..b35d115692 100644
--- a/src/cpu/amd/agesa/family15tn/fixme.c
+++ b/src/cpu/amd/agesa/family15tn/fixme.c
@@ -72,13 +72,6 @@ void amd_initmmio(void)
MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
- /*
- Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
- */
- LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
- MsrReg = MsrReg | 0x0000400000000000;
- LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
-
/* Set ROM cache onto WP to decrease post time */
MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);