AMD Fam15tn: Split DSDT into common sections

Split the Parmer, Family 15tn, and Hudson DSDT into groups.  This splits
the DSDT table into includable ASL files which carry details specific
to the Family 15tn APU, the Parmer platform, and the Hudson FCH.  The
dsdt.asl file in the mainboard directory contains only #include
references to the appropriate files.

Initially, this split was done by moving each piece of functionality
into its own file (e.g. IRQ routing and mapping, processor tree, sleep
states and sleep methods, etc.) and those pieces were #included in
dsdt.asl to ensure an exact match (via acpidump/acpixtract/iasl -d)
with the extant version of the table.  Once the new tables were found
to exactly match the existing tables, the pieces were rearranged into
reasonable groups (e.g. fch.asl, northbridge.asl, pci_int.asl, etc.).

Some include files have no content but are left as a template for
other platforms and as placeholders for completing the ACPI
implementation for Parmer (e.g. thermal.asl, superio.asl, ide.asl,
sata.asl, etc.).

Change-Id: I098b0c5ca27629da9bc1cff1e6ba9fa6703e2710
Signed-off-by: Steve Goodrich <steve.goodrich@se-eng.com>
Reviewed-on: http://review.coreboot.org/3629
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>

1 files changed, 83 insertions, 0 deletions

diff --git a/src/cpu/amd/agesa/family15tn/acpi/cpu.asl b/src/cpu/amd/agesa/family15tn/acpi/cpu.asl
new file mode 100755
index 0000000000..dc86df54e0
--- /dev/null
+++ b/src/cpu/amd/agesa/family15tn/acpi/cpu.asl
@@ -0,0 +1,83 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+	/*
+	 * Processor Object
+	 *
+	 */
+	Scope (\_PR) {		/* define processor scope */
+		Processor(
+			P000,		/* name space name */
+			0,		/* Unique number for this processor */
+			0x810,		/* PBLK system I/O address !hardcoded! */
+			0x06		/* PBLKLEN for boot processor */
+			) {
+		}
+
+		Processor(
+			P001,		/* name space name */
+			1,		/* Unique number for this processor */
+			0x0810,		/* PBLK system I/O address !hardcoded! */
+			0x06		/* PBLKLEN for boot processor */
+			) {
+		}
+		Processor(
+			P002,		/* name space name */
+			2,		/* Unique number for this processor */
+			0x0810,		/* PBLK system I/O address !hardcoded! */
+			0x06		/* PBLKLEN for boot processor */
+			) {
+		}
+		Processor(
+			P003,		/* name space name */
+			3,		/* Unique number for this processor */
+			0x0810,		/* PBLK system I/O address !hardcoded! */
+			0x06		/* PBLKLEN for boot processor */
+			) {
+		}
+		Processor(
+			P004,		/* name space name */
+			4,		/* Unique number for this processor */
+			0x0810,		/* PBLK system I/O address !hardcoded! */
+			0x06		/* PBLKLEN for boot processor */
+			) {
+		}
+		Processor(
+			P005,		/* name space name */
+			5,		/* Unique number for this processor */
+			0x0810,		/* PBLK system I/O address !hardcoded! */
+			0x06		/* PBLKLEN for boot processor */
+			) {
+		}
+		Processor(
+			P006,		/* name space name */
+			6,		/* Unique number for this processor */
+			0x0810,		/* PBLK system I/O address !hardcoded! */
+			0x06		/* PBLKLEN for boot processor */
+			) {
+		}
+		Processor(
+			P007,		/* name space name */
+			7,		/* Unique number for this processor */
+			0x0810,		/* PBLK system I/O address !hardcoded! */
+			0x06		/* PBLKLEN for boot processor */
+			) {
+		}
+	} /* End _PR scope */
+