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authorEdward O'Callaghan <eocallaghan@alterapraxis.com>2014-11-21 12:48:39 +1100
committerEdward O'Callaghan <eocallaghan@alterapraxis.com>2014-11-22 15:37:28 +0100
commitd7e5008bdfc15386333d7d6b82e69cc50e99b39b (patch)
tree3fe2d3b13eef7163595736646ad16700dfb53a6b /src/cpu/amd/agesa
parent20a41ae80bea48db1225bbfba67ffb17ec89b318 (diff)
downloadcoreboot-d7e5008bdfc15386333d7d6b82e69cc50e99b39b.tar.xz
cpu/amd/agesa/family1{0,2}: Fix indent and sync closer together
Change-Id: If1ca90aa8050fc1b2e1c98e0fb669de1d155a949 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7543 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/cpu/amd/agesa')
-rw-r--r--src/cpu/amd/agesa/family10/model_10_init.c1
-rw-r--r--src/cpu/amd/agesa/family12/model_12_init.c96
2 files changed, 49 insertions, 48 deletions
diff --git a/src/cpu/amd/agesa/family10/model_10_init.c b/src/cpu/amd/agesa/family10/model_10_init.c
index 1d44dbf7d1..3c8c7df0de 100644
--- a/src/cpu/amd/agesa/family10/model_10_init.c
+++ b/src/cpu/amd/agesa/family10/model_10_init.c
@@ -40,6 +40,7 @@ static void model_10_init(device_t dev)
u8 i;
msr_t msr;
+
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
u32 siblings;
#endif
diff --git a/src/cpu/amd/agesa/family12/model_12_init.c b/src/cpu/amd/agesa/family12/model_12_init.c
index f63bddc049..e2ae7b77ad 100644
--- a/src/cpu/amd/agesa/family12/model_12_init.c
+++ b/src/cpu/amd/agesa/family12/model_12_init.c
@@ -37,81 +37,81 @@
static void model_12_init(device_t dev)
{
- printk(BIOS_DEBUG, "Model 12 Init - a no-op.\n");
+ printk(BIOS_DEBUG, "Model 12 Init - a no-op.\n");
- u8 i;
- msr_t msr;
+ u8 i;
+ msr_t msr;
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
- u32 siblings;
+ u32 siblings;
#endif
// struct node_core_id id;
// id = get_node_core_id(read_nb_cfg_54()); /* nb_cfg_54 can not be set */
// printk(BIOS_DEBUG, "nodeid = %02d, coreid = %02d\n", id.nodeid, id.coreid);
- /* Turn on caching if we haven't already */
- x86_enable_cache();
- amd_setup_mtrrs();
- x86_mtrr_check();
+ /* Turn on caching if we haven't already */
+ x86_enable_cache();
+ amd_setup_mtrrs();
+ x86_mtrr_check();
- disable_cache();
+ disable_cache();
- /* zero the machine check error status registers */
- msr.lo = 0;
- msr.hi = 0;
- for (i = 0; i < 5; i++) {
- wrmsr(MCI_STATUS + (i * 4), msr);
- }
+ /* zero the machine check error status registers */
+ msr.lo = 0;
+ msr.hi = 0;
+ for (i = 0; i < 5; i++) {
+ wrmsr(MCI_STATUS + (i * 4), msr);
+ }
- enable_cache();
+ enable_cache();
- /* Enable the local cpu apics */
- setup_lapic();
+ /* Enable the local cpu apics */
+ setup_lapic();
- /* Set the processor name string */
-// init_processor_name();
+ /* Set the processor name string */
+ // init_processor_name();
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
- siblings = cpuid_ecx(0x80000008) & 0xff;
-
- if (siblings > 0) {
- msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
- msr.lo |= 1 << 28;
- wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
-
- msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
- msr.hi |= 1 << (33 - 32);
- wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
- }
- printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
+ siblings = cpuid_ecx(0x80000008) & 0xff;
+
+ if (siblings > 0) {
+ msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
+ msr.lo |= 1 << 28;
+ wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
+
+ msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
+ msr.hi |= 1 << (33 - 32);
+ wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
+ }
+ printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
#endif
- /* DisableCf8ExtCfg */
- msr = rdmsr(NB_CFG_MSR);
- msr.hi &= ~(1 << (46 - 32));
- wrmsr(NB_CFG_MSR, msr);
+ /* DisableCf8ExtCfg */
+ msr = rdmsr(NB_CFG_MSR);
+ msr.hi &= ~(1 << (46 - 32));
+ wrmsr(NB_CFG_MSR, msr);
- /* Write protect SMM space with SMMLOCK. */
- msr = rdmsr(HWCR_MSR);
- msr.lo |= (1 << 0);
- wrmsr(HWCR_MSR, msr);
+ /* Write protect SMM space with SMMLOCK. */
+ msr = rdmsr(HWCR_MSR);
+ msr.lo |= (1 << 0);
+ wrmsr(HWCR_MSR, msr);
}
static struct device_operations cpu_dev_ops = {
- .init = model_12_init,
+ .init = model_12_init,
};
static struct cpu_device_id cpu_table[] = {
- { X86_VENDOR_AMD, 0x300f00 }, /* LN1_A0x */
- { X86_VENDOR_AMD, 0x300f01 }, /* LN1_A1x */
- { X86_VENDOR_AMD, 0x300f10 }, /* LN1_B0x */
- { X86_VENDOR_AMD, 0x300f20 }, /* LN2_B0x */
- { 0, 0 },
+ { X86_VENDOR_AMD, 0x300f00 }, /* LN1_A0x */
+ { X86_VENDOR_AMD, 0x300f01 }, /* LN1_A1x */
+ { X86_VENDOR_AMD, 0x300f10 }, /* LN1_B0x */
+ { X86_VENDOR_AMD, 0x300f20 }, /* LN2_B0x */
+ { 0, 0 },
};
static const struct cpu_driver model_12 __cpu_driver = {
- .ops = &cpu_dev_ops,
- .id_table = cpu_table,
+ .ops = &cpu_dev_ops,
+ .id_table = cpu_table,
};