AMD: Isolate AGESA and PI build environments

To backport features introduced with recent Chromebooks and/or Intel
boards in general, heavy work on the AMD AGESA platform infrastructure
is required. With the AGESA PI available in binary form only, community
members have little means to verify, debug and develop for the said
platforms.

Thus it makes sense to fork the existing agesawrapper interfaces, to give
AMD PI platforms a clean and independent sandbox. New directory layout
reflects the separation already taken place under 3rdparty/ and vendorcode/.

Change-Id: Ib60861266f8a70666617dde811663f2d5891a9e0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7149
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Tested-by: build bot (Jenkins)

8 files changed, 1 insertions, 345 deletions

diff --git a/src/cpu/amd/agesa/00730F01/Kconfig b/src/cpu/amd/agesa/00730F01/Kconfig
deleted file mode 100644
index ccc44d6c5d..0000000000
--- a/src/cpu/amd/agesa/00730F01/Kconfig
+++ /dev/null
@@ -1,69 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2012 Advanced Micro Devices, Inc.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-#
-
-config CPU_AMD_AGESA_00730F01
-	bool
-	select PCI_IO_CFG_EXT
-	select X86_AMD_FIXED_MTRRS
-
-if CPU_AMD_AGESA_00730F01
-
-config CPU_ADDR_BITS
-	int
-	default 40
-
-config CPU_SOCKET_TYPE
-	hex
-	default 0x10
-
-# DDR2 and REG
-config DIMM_SUPPORT
-	hex
-	default 0x0104
-
-config EXT_RT_TBL_SUPPORT
-	bool
-	default n
-
-config EXT_CONF_SUPPORT
-	bool
-	default n
-
-config CBB
-	hex
-	default 0x0
-
-config CDB
-	hex
-	default 0x18
-
-config XIP_ROM_BASE
-	hex
-	default 0xfff80000
-
-config XIP_ROM_SIZE
-	hex
-	default 0x100000
-
-config HIGH_SCRATCH_MEMORY_SIZE
-	hex
-	# Assume the maximum size of stack as (0xA0000 - 0x30000 + 0x1000)
-	default 0xA1000
-
-endif
diff --git a/src/cpu/amd/agesa/00730F01/Makefile.inc b/src/cpu/amd/agesa/00730F01/Makefile.inc
deleted file mode 100644
index fba21854e7..0000000000
--- a/src/cpu/amd/agesa/00730F01/Makefile.inc
+++ /dev/null
@@ -1,29 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2012 Advanced Micro Devices, Inc.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-#
-
-ramstage-y += chip_name.c
-ramstage-y += model_16_init.c
-
-subdirs-y += ../../mtrr
-subdirs-y += ../../../x86/tsc
-subdirs-y += ../../../x86/lapic
-subdirs-y += ../../../x86/cache
-subdirs-y += ../../../x86/mtrr
-subdirs-y += ../../../x86/pae
-subdirs-y += ../../../x86/smm
diff --git a/src/cpu/amd/agesa/00730F01/acpi/cpu.asl b/src/cpu/amd/agesa/00730F01/acpi/cpu.asl
deleted file mode 100644
index dc86df54e0..0000000000
--- a/src/cpu/amd/agesa/00730F01/acpi/cpu.asl
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Sage Electronic Engineering, LLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-	/*
-	 * Processor Object
-	 *
-	 */
-	Scope (\_PR) {		/* define processor scope */
-		Processor(
-			P000,		/* name space name */
-			0,		/* Unique number for this processor */
-			0x810,		/* PBLK system I/O address !hardcoded! */
-			0x06		/* PBLKLEN for boot processor */
-			) {
-		}
-
-		Processor(
-			P001,		/* name space name */
-			1,		/* Unique number for this processor */
-			0x0810,		/* PBLK system I/O address !hardcoded! */
-			0x06		/* PBLKLEN for boot processor */
-			) {
-		}
-		Processor(
-			P002,		/* name space name */
-			2,		/* Unique number for this processor */
-			0x0810,		/* PBLK system I/O address !hardcoded! */
-			0x06		/* PBLKLEN for boot processor */
-			) {
-		}
-		Processor(
-			P003,		/* name space name */
-			3,		/* Unique number for this processor */
-			0x0810,		/* PBLK system I/O address !hardcoded! */
-			0x06		/* PBLKLEN for boot processor */
-			) {
-		}
-		Processor(
-			P004,		/* name space name */
-			4,		/* Unique number for this processor */
-			0x0810,		/* PBLK system I/O address !hardcoded! */
-			0x06		/* PBLKLEN for boot processor */
-			) {
-		}
-		Processor(
-			P005,		/* name space name */
-			5,		/* Unique number for this processor */
-			0x0810,		/* PBLK system I/O address !hardcoded! */
-			0x06		/* PBLKLEN for boot processor */
-			) {
-		}
-		Processor(
-			P006,		/* name space name */
-			6,		/* Unique number for this processor */
-			0x0810,		/* PBLK system I/O address !hardcoded! */
-			0x06		/* PBLKLEN for boot processor */
-			) {
-		}
-		Processor(
-			P007,		/* name space name */
-			7,		/* Unique number for this processor */
-			0x0810,		/* PBLK system I/O address !hardcoded! */
-			0x06		/* PBLKLEN for boot processor */
-			) {
-		}
-	} /* End _PR scope */
-
diff --git a/src/cpu/amd/agesa/00730F01/chip_name.c b/src/cpu/amd/agesa/00730F01/chip_name.c
deleted file mode 100644
index 7a1c06ccff..0000000000
--- a/src/cpu/amd/agesa/00730F01/chip_name.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-
-struct chip_operations cpu_amd_agesa_00730F01_ops = {
-	CHIP_NAME("AMD CPU Family 16h")
-};
diff --git a/src/cpu/amd/agesa/00730F01/model_16_init.c b/src/cpu/amd/agesa/00730F01/model_16_init.c
deleted file mode 100644
index 8053fd1f06..0000000000
--- a/src/cpu/amd/agesa/00730F01/model_16_init.c
+++ /dev/null
@@ -1,133 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <string.h>
-#include <cpu/x86/msr.h>
-#include <cpu/x86/pae.h>
-#include <pc80/mc146818rtc.h>
-#include <cpu/x86/lapic.h>
-
-#include <cpu/cpu.h>
-#include <cpu/x86/cache.h>
-#include <cpu/x86/mtrr.h>
-#include <cpu/amd/amdfam16.h>
-#include <arch/acpi.h>
-#if CONFIG_HAVE_ACPI_RESUME
-#include <cpu/amd/agesa/s3_resume.h>
-#endif
-
-static void model_16_init(device_t dev)
-{
-	printk(BIOS_DEBUG, "Model 16 Init.\n");
-
-	u8 i;
-	msr_t msr;
-	int msrno;
-#if CONFIG_LOGICAL_CPUS
-	u32 siblings;
-#endif
-
-	//x86_enable_cache();
-	//amd_setup_mtrrs();
-	//x86_mtrr_check();
-	disable_cache ();
-	/* Enable access to AMD RdDram and WrDram extension bits */
-	msr = rdmsr(SYSCFG_MSR);
-	msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
-	msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn;
-	wrmsr(SYSCFG_MSR, msr);
-
-	// BSP: make a0000-bffff UC, c0000-fffff WB, same as OntarioApMtrrSettingsList for APs
-	msr.lo = msr.hi = 0;
-	wrmsr (0x259, msr);
-	msr.lo = msr.hi = 0x1e1e1e1e;
-	wrmsr(0x250, msr);
-	wrmsr(0x258, msr);
-	for (msrno = 0x268; msrno <= 0x26f; msrno++)
-		wrmsr (msrno, msr);
-
-	msr = rdmsr(SYSCFG_MSR);
-	msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
-	msr.lo |= SYSCFG_MSR_MtrrFixDramEn;
-	wrmsr(SYSCFG_MSR, msr);
-
-#if CONFIG_HAVE_ACPI_RESUME
-	if (acpi_slp_type == 3)
-		restore_mtrr();
-#endif
-
-	x86_mtrr_check();
-	x86_enable_cache();
-
-	/* zero the machine check error status registers */
-	msr.lo = 0;
-	msr.hi = 0;
-	for (i = 0; i < 6; i++) {
-		wrmsr(MCI_STATUS + (i * 4), msr);
-	}
-
-
-	/* Enable the local cpu apics */
-	setup_lapic();
-
-#if CONFIG_LOGICAL_CPUS
-	siblings = cpuid_ecx(0x80000008) & 0xff;
-
-	if (siblings > 0) {
-		msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
-		msr.lo |= 1 << 28;
-		wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
-
-		msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
-		msr.hi |= 1 << (33 - 32);
-		wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
-	}
-	printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
-#endif
-
-	/* DisableCf8ExtCfg */
-	msr = rdmsr(NB_CFG_MSR);
-	msr.hi &= ~(1 << (46 - 32));
-	wrmsr(NB_CFG_MSR, msr);
-
-
-	/* Write protect SMM space with SMMLOCK. */
-	msr = rdmsr(HWCR_MSR);
-	msr.lo |= (1 << 0);
-	wrmsr(HWCR_MSR, msr);
-}
-
-static struct device_operations cpu_dev_ops = {
-	.init = model_16_init,
-};
-
-static struct cpu_device_id cpu_table[] = {
-	{ X86_VENDOR_AMD, 0x730f00 },	  /* ML-A0, Guess, TODO: */
-	{ 0, 0 },
-};
-
-static const struct cpu_driver model_16 __cpu_driver = {
-	.ops      = &cpu_dev_ops,
-	.id_table = cpu_table,
-};
diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig
index d288fef177..fcba0cfdb2 100644
--- a/src/cpu/amd/agesa/Kconfig
+++ b/src/cpu/amd/agesa/Kconfig
@@ -25,7 +25,6 @@ config CPU_AMD_AGESA
 	default y if CPU_AMD_AGESA_FAMILY15
 	default y if CPU_AMD_AGESA_FAMILY15_TN
 	default y if CPU_AMD_AGESA_FAMILY16_KB
-	default y if CPU_AMD_AGESA_00730F01
 	default n
 	select ARCH_BOOTBLOCK_X86_32
 	select ARCH_ROMSTAGE_X86_32
@@ -85,5 +84,4 @@ source src/cpu/amd/agesa/family14/Kconfig
 source src/cpu/amd/agesa/family15/Kconfig
 source src/cpu/amd/agesa/family15tn/Kconfig
 source src/cpu/amd/agesa/family16kb/Kconfig
-source src/cpu/amd/agesa/00730F01/Kconfig
 
diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc
index 800f8e7452..beba040ef4 100644
--- a/src/cpu/amd/agesa/Makefile.inc
+++ b/src/cpu/amd/agesa/Makefile.inc
@@ -22,7 +22,6 @@ subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += family14
 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15) += family15
 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) += family15tn
 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) += family16kb
-subdirs-$(CONFIG_CPU_AMD_AGESA_00730F01) += 00730F01
 
 romstage-y += s3_resume.c
 ramstage-y += s3_resume.c
diff --git a/src/cpu/amd/agesa/amd_late_init.c b/src/cpu/amd/agesa/amd_late_init.c
index cab03a3096..4fa2e4e8bc 100644
--- a/src/cpu/amd/agesa/amd_late_init.c
+++ b/src/cpu/amd/agesa/amd_late_init.c
@@ -31,9 +31,6 @@
 #include <sb_cimx.h>
 #endif
 
-#define NORTHBRIDGE_00700F00 IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY_16KB)
-#define NORTHBRIDGE_00730F01 IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA_00730F01)
-
 static void agesawrapper_post_device(void *unused)
 {
 	if (acpi_is_wakeup_s3())
@@ -41,7 +38,7 @@ static void agesawrapper_post_device(void *unused)
 
 	AGESAWRAPPER(amdinitlate);
 
-#if (NORTHBRIDGE_00700F00) || (NORTHBRIDGE_00730F01)
+#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY_16KB)
 	device_t dev;
 	u32 value;
 	dev = dev_find_slot(0, PCI_DEVFN(0, 0)); /* clear IoapicSbFeatureEn */