diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-06-30 07:34:36 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-07-14 19:43:03 +0200 |
| commit | 9f0a2be1658cf6d329aefac2660a53a465312468 (patch) | |
| tree | 7efd750712c5c829761e065605cee3b4b3f8b788 /src/cpu/amd/agesa | |
| parent | 1110495de926db4b21b9969da522e5270c67f115 (diff) | |
| download | coreboot-9f0a2be1658cf6d329aefac2660a53a465312468.tar.xz | |
AMD SPI: Optimise for longer writes
Leave it to the implementation of flash->write() to split the writes
to match SPI controller and SPI flash part restrictions. This allows
for some optimisation for auto-address-increment (AAI) commands.
Kconfig AMD_SB_SPI_TX_LEN can be kept as local.
Change-Id: I4a8bc55ab7eb0eeda8f25003a8f5ff2a643ab7a7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6164
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/cpu/amd/agesa')
| -rw-r--r-- | src/cpu/amd/agesa/spi.c | 7 |
1 files changed, 1 insertions, 6 deletions
diff --git a/src/cpu/amd/agesa/spi.c b/src/cpu/amd/agesa/spi.c index 5631053148..1c652fd295 100644 --- a/src/cpu/amd/agesa/spi.c +++ b/src/cpu/amd/agesa/spi.c @@ -40,12 +40,7 @@ void spi_SaveS3info(u32 pos, u32 size, u8 *buf, u32 len) flash->erase(flash, pos, size); flash->write(flash, pos, sizeof(len), &len); - - u32 nvram_pos; - for (nvram_pos = 0; nvram_pos < len - CONFIG_AMD_SB_SPI_TX_LEN; nvram_pos += CONFIG_AMD_SB_SPI_TX_LEN) { - flash->write(flash, nvram_pos + pos + 4, CONFIG_AMD_SB_SPI_TX_LEN, (u8 *)(buf + nvram_pos)); - } - flash->write(flash, nvram_pos + pos + 4, len % CONFIG_AMD_SB_SPI_TX_LEN, (u8 *)(buf + nvram_pos)); + flash->write(flash, pos + sizeof(len), len, buf); flash->spi->rw = SPI_WRITE_FLAG; spi_release_bus(flash->spi); |