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authorKyösti Mälkki <kyosti.malkki@gmail.com>2017-09-01 19:23:35 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2017-10-05 13:23:27 +0000
commit0e1ea279d025887c6904b4bb559c7165b44c6dec (patch)
tree61e6532864340fed66237883e70f80dcddb251e6 /src/cpu/amd/agesa
parent6287a69530133b63946e5c30b07a3c29fc3a25d9 (diff)
downloadcoreboot-0e1ea279d025887c6904b4bb559c7165b44c6dec.tar.xz
AGESA vendorcode: Add ENABLE_MRC_CACHE option
When selected, try to store and restore memory training results from/to SPI flash. This change only pulls in the required parts from vendorcode for the build. Change-Id: I12880237be494c71e1d4836abd2d4b714ba87762 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/cpu/amd/agesa')
-rw-r--r--src/cpu/amd/agesa/Kconfig8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig
index 4605dd3ba9..602a9b0528 100644
--- a/src/cpu/amd/agesa/Kconfig
+++ b/src/cpu/amd/agesa/Kconfig
@@ -72,6 +72,14 @@ config DCACHE_RAM_SIZE
hex
default 0x10000
+config ENABLE_MRC_CACHE
+ bool "Use cached memory configuration"
+ default n
+ select SPI_FLASH
+ help
+ Try to restore memory training results
+ from non-volatile memory.
+
config S3_DATA_POS
hex
default 0xFFFF0000