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| author | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2014-04-12 21:57:18 -0500 |
|---|---|---|
| committer | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2014-04-16 23:42:00 +0200 |
| commit | 53072d869ad9234781b5a479dfcc9a9288723da6 (patch) | |
| tree | 533bb1f9cb5b97fd8d3f22d49368b47831b464f1 /src/cpu/amd/agesa | |
| parent | 342ac64a5d6f5ab639fb140ae69f9b3597878cba (diff) | |
| download | coreboot-53072d869ad9234781b5a479dfcc9a9288723da6.tar.xz | |
cpu/amd/agesa/family15tn: Add initial support for SMM mode
This is the minimal setup needed to be able to execute SMI handlers.
Only support for ASEG handlers is added, which should be sufficient
for Trinity (up to 4 cores).
There are a few hacks which need to be introduced in generic code in
order to make this work properly, but these hacks are self-contained.
They are a not a result of any special needs of this CPU, but rather
from a poorly designed infrastructure. Comments are added to explain
how such code could be refactored in the future.
Change-Id: Iefd4ae17cf0206cae8848cadba3a12cbe3b2f8b6
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5493
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
Diffstat (limited to 'src/cpu/amd/agesa')
| -rw-r--r-- | src/cpu/amd/agesa/family15tn/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/cpu/amd/agesa/family15tn/model_15_init.c | 16 |
2 files changed, 17 insertions, 0 deletions
diff --git a/src/cpu/amd/agesa/family15tn/Makefile.inc b/src/cpu/amd/agesa/family15tn/Makefile.inc index a5a707167f..19a2f0f298 100644 --- a/src/cpu/amd/agesa/family15tn/Makefile.inc +++ b/src/cpu/amd/agesa/family15tn/Makefile.inc @@ -21,6 +21,7 @@ ramstage-y += chip_name.c ramstage-y += model_15_init.c subdirs-y += ../../mtrr +subdirs-y += ../../smm subdirs-y += ../../../x86/tsc subdirs-y += ../../../x86/lapic subdirs-y += ../../../x86/cache diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c index f396201181..467a3012df 100644 --- a/src/cpu/amd/agesa/family15tn/model_15_init.c +++ b/src/cpu/amd/agesa/family15tn/model_15_init.c @@ -19,6 +19,7 @@ #include <console/console.h> #include <cpu/x86/msr.h> +#include <cpu/x86/smm.h> #include <cpu/amd/mtrr.h> #include <device/device.h> #include <string.h> @@ -43,6 +44,7 @@ static void model_15_init(device_t dev) u8 i; msr_t msr; int msrno; + unsigned int cpu_idx; #if CONFIG_LOGICAL_CPUS u32 siblings; #endif @@ -110,6 +112,20 @@ static void model_15_init(device_t dev) msr.hi &= ~(1 << (46 - 32)); wrmsr(NB_CFG_MSR, msr); + if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { + cpu_idx = cpu_info()->index; + printk(BIOS_INFO, "Initializing SMM for CPU %u\n", cpu_idx); + + /* Set SMM base address for this CPU */ + msr = rdmsr(MSR_SMM_BASE); + msr.lo = SMM_BASE - (cpu_idx * 0x400); + wrmsr(MSR_SMM_BASE, msr); + + /* Enable the SMM memory window */ + msr = rdmsr(MSR_SMM_MASK); + msr.lo |= (1 << 0); /* Enable ASEG SMRAM Range */ + wrmsr(MSR_SMM_MASK, msr); + } /* Write protect SMM space with SMMLOCK. */ msr = rdmsr(HWCR_MSR); |