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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-11-23 21:29:26 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-04-05 15:02:03 +0200 |
| commit | 1779d534e5b6e01e2aabfb30aa369e0aebe28488 (patch) | |
| tree | c003cee96fabc2b6161a566679943b9ba2a57acc /src/cpu/amd/agesa | |
| parent | df7ff31c5985d9c8e37c9f780c02c61e652181c0 (diff) | |
| download | coreboot-1779d534e5b6e01e2aabfb30aa369e0aebe28488.tar.xz | |
AGESA: BIST is already preserved
Officialy we enter with BIST in %eax, but %ebp is old backup register.
Note that post_code() destroys %al.
Change-Id: I77b9a80aac11ae301fdda71c2a20803d7a5fb888
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18625
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/cpu/amd/agesa')
| -rw-r--r-- | src/cpu/amd/agesa/cache_as_ram.inc | 15 |
1 files changed, 7 insertions, 8 deletions
diff --git a/src/cpu/amd/agesa/cache_as_ram.inc b/src/cpu/amd/agesa/cache_as_ram.inc index 2a9beb8aa4..1258d154c3 100644 --- a/src/cpu/amd/agesa/cache_as_ram.inc +++ b/src/cpu/amd/agesa/cache_as_ram.inc @@ -28,7 +28,6 @@ /* * XMM map: - * xmm0: BIST */ .code32 @@ -36,6 +35,9 @@ cache_as_ram_setup: + /* Preserve BIST. */ + movl %eax, %ebp + post_code(0xa0) /* enable SSE2 128bit instructions */ @@ -45,11 +47,9 @@ cache_as_ram_setup: orl $(3<<9), %eax movl %eax, %cr4 - /* Save the BIST result */ - cvtsi2sd %ebp, %xmm0 - post_code(0xa1) + /* NOTE: %ebx, %ebp are preserved in AMD_ENABLE_STACK. */ AMD_ENABLE_STACK /* Align the stack. */ @@ -100,16 +100,15 @@ cache_as_ram_setup: #endif - call early_all_cores + /* Calling conventions preserve BIST in %ebp. */ - /* Restore the BIST result */ - cvtsd2si %xmm0, %edx + call early_all_cores /* Must maintain 16-byte stack alignment here. */ pushl $0x0 pushl $0x0 pushl $0x0 - pushl %edx /* bist */ + pushl %ebp call romstage_main /* Should never see this postcode */ |