diff options
author | Yinghai Lu <yinghailu@gmail.com> | 2005-07-08 02:49:49 +0000 |
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committer | Yinghai Lu <yinghailu@gmail.com> | 2005-07-08 02:49:49 +0000 |
commit | 13f1c2af8be2cd7f7e99a678f5d428a65b771811 (patch) | |
tree | 27cad5581f1fa150f573149d48e82f70ba1b1d9f /src/cpu/amd/car | |
parent | 14cde9e96a777f9d75016a13b23fab0480515f58 (diff) | |
download | coreboot-13f1c2af8be2cd7f7e99a678f5d428a65b771811.tar.xz |
eric patch
1. x86_setup_mtrr take address bit.
2. generic ht, pcix, pcie beidge...
3. scan bus and reset_bus
4. ht read ctrl to decide if the ht chain
is ready
5. Intel e7520 and e7525 support
6. new ich5r support
7. intel sb 6300 support.
yhlu patch
1. split x86_setup_mtrrs to fixed and var
2. if (resource->flags & IORESOURCE_FIXED ) return; in device.c pick_largest_resource
3. in_conherent.c K8_SCAN_PCI_BUS
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1982 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/amd/car')
-rw-r--r-- | src/cpu/amd/car/cache_as_ram_post.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/cpu/amd/car/cache_as_ram_post.c b/src/cpu/amd/car/cache_as_ram_post.c index 66ca9fdf96..6a129b258a 100644 --- a/src/cpu/amd/car/cache_as_ram_post.c +++ b/src/cpu/amd/car/cache_as_ram_post.c @@ -1,4 +1,5 @@ /* by yhlu 6.2005 */ +/* be warned, this file will be used other cores and core0/node0 */ __asm__ volatile ( /* FIXME : backup stack in CACHE_AS_RAM into mmx and sse and after we get STACK up, we restore that. |