diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-15 15:37:30 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-18 08:09:21 +0000 |
| commit | 184a1176f3de05bd8f09ab16fff91b8b75a5a1c2 (patch) | |
| tree | c0ad4f138c383d4e8f7daee2b20dd7b7df6693f4 /src/cpu/amd/car | |
| parent | 126d4198a9739f07fe456da27aef10076b955185 (diff) | |
| download | coreboot-184a1176f3de05bd8f09ab16fff91b8b75a5a1c2.tar.xz | |
amdfam10-15: Rename DCACHE_BSP_STACK_SIZE
The original name DCACHE_BSP_STACK_SIZE will be exclusively
used to define the fixed size of BSP stack when it is located
near the beginning of CAR region. This implementation has the
stack located at the very end of CAR region.
Remove other fam10-15 exclusive configs from global space.
Change-Id: I8b92891be2ed62944a9eddde39ed20a12f4875c0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/cpu/amd/car')
| -rw-r--r-- | src/cpu/amd/car/cache_as_ram.inc | 4 | ||||
| -rw-r--r-- | src/cpu/amd/car/post_cache_as_ram.c | 6 |
2 files changed, 5 insertions, 5 deletions
diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index f923a47db4..d923377b89 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -22,8 +22,8 @@ #define CacheSize CONFIG_DCACHE_RAM_SIZE #define CacheBase CONFIG_DCACHE_RAM_BASE -#define CacheSizeBSPStack CONFIG_DCACHE_BSP_STACK_SIZE -#define CacheSizeBSPSlush CONFIG_DCACHE_BSP_STACK_SLUSH +#define CacheSizeBSPStack CONFIG_DCACHE_BSP_TOP_STACK_SIZE +#define CacheSizeBSPSlush CONFIG_DCACHE_BSP_TOP_STACK_SLUSH /* For CAR with Fam10h. */ #define CacheSizeAPStack CONFIG_DCACHE_AP_STACK_SIZE diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 50ed657f42..aa8222bc9d 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -131,9 +131,9 @@ asmlinkage void *post_cache_as_ram(void) * boundary during romstage execution */ volatile uint32_t *lower_stack_boundary; - lower_stack_boundary = - (void *)((CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE) - - CONFIG_DCACHE_BSP_STACK_SIZE); + lower_stack_boundary = (void *)((CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE) - + CONFIG_DCACHE_BSP_TOP_STACK_SIZE); + if ((*lower_stack_boundary) != 0xdeadbeef) printk(BIOS_WARNING, "BSP overran lower stack boundary. Undefined behaviour may result!\n"); |