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authorKyösti Mälkki <kyosti.malkki@gmail.com>2016-11-20 11:03:13 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2016-12-01 05:50:52 +0100
commit187543c90da824198a7da2b531665f4d2dece243 (patch)
tree48ac0247b7f86f2a289bb6e15d3247f1dbd8467f /src/cpu/amd/car
parentcc37bbd7acaaa060fa272115aa077baabac402c4 (diff)
downloadcoreboot-187543c90da824198a7da2b531665f4d2dece243.tar.xz
AMD binaryPI: Switch to MMCONF_SUPPORT_DEFAULT
Vendorcode always does PCI MMCONF access once it is enabled via MSR. In coreboot proper, we don't give opportunity to make pci_read/write calls before PCI MMCONF is enabled via MSR. This happens early in romstage amd_initmmio() for all cores. Change-Id: Id6ec25706b52441259e7dc1582f9a4ce8b154083 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17534 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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