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authorYinghai Lu <yinghailu@gmail.com>2005-12-07 19:02:45 +0000
committerYinghai Lu <yinghailu@gmail.com>2005-12-07 19:02:45 +0000
commitc3b360022258c4cfb7413cb88457f0c10ab396fa (patch)
treefddacc5b55d96281fdc237d1445a159df0dfaa4b /src/cpu/amd/car
parent73cc74e4f08fbd41d2025fd20abf9427d94e618a (diff)
downloadcoreboot-c3b360022258c4cfb7413cb88457f0c10ab396fa.tar.xz
use CONFIG_LB_MEM_TOPK instead 1M hardcode from issue 50
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2139 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/amd/car')
-rw-r--r--src/cpu/amd/car/clear_1m_ram.c88
1 files changed, 46 insertions, 42 deletions
diff --git a/src/cpu/amd/car/clear_1m_ram.c b/src/cpu/amd/car/clear_1m_ram.c
index 80b215e502..eabb6db0fe 100644
--- a/src/cpu/amd/car/clear_1m_ram.c
+++ b/src/cpu/amd/car/clear_1m_ram.c
@@ -3,54 +3,58 @@
static inline __attribute__((always_inline)) void clear_1m_ram(void)
{
__asm__ volatile (
+ /* disable cache */
+ "movl %cr0, %eax\n\t"
+ "orl $(0x1<<30),%eax\n\t"
+ "movl %eax, %cr0\n\t"
+ );
- /* disable cache */
- "movl %cr0, %eax\n\t"
- "orl $(0x1<<30),%eax\n\t"
- "movl %eax, %cr0\n\t"
-
- /* enable caching for first 1M using variable mtrr */
- "movl $0x200, %ecx\n\t"
- "xorl %edx, %edx\n\t"
- "movl $(0 | 1), %eax\n\t"
-// "movl $(0 | MTRR_TYPE_WRCOMB), %eax\n\t"
- "wrmsr\n\t"
-
- "movl $0x201, %ecx\n\t"
- "movl $0x0000000f, %edx\n\t"
- "movl $((~(( 0 + 0x100000) - 1)) | 0x800), %eax\n\t"
- "wrmsr\n\t"
+ /* enable caching for first 1M using variable mtrr */
+ __asm__ volatile (
+ "wrmsr"
+ : /* No outputs */
+ : "c" (0x200), "a" (0 | MTRR_TYPE_WRCOMB), "d" (0)
+ );
- /* clear the first 1M */
- "movl $0x0, %edi\n\t"
- "cld\n\t"
- "movl $(0x100000>>2), %ecx\n\t"
- "xorl %eax, %eax\n\t"
- "rep stosl\n\t"
+ __asm__ volatile (
+ "wrmsr"
+ : /* No outputs */
+ : "c" (0x201), "a" ((~(( 0 + (CONFIG_LB_MEM_TOPK<<10) ) -1)) | 0x800), "d" (0x0000000f)
+ );
- /* disable cache */
- "movl %cr0, %eax\n\t"
- "orl $(0x1<<30),%eax\n\t"
- "movl %eax, %cr0\n\t"
+ __asm__ volatile(
+ /* clear the first 1M */
+ "cld\n\t"
+ "rep stosl\n\t"
+ :
+ : "a"(0), "D"(0) ,"c" ((CONFIG_LB_MEM_TOPK<<10)>>2)
+ );
+
+ __asm__ volatile (
+ /* disable cache */
+ "movl %cr0, %eax\n\t"
+ "orl $(0x1<<30),%eax\n\t"
+ "movl %eax, %cr0\n\t"
+ );
/* enable caching for first 1M using variable mtrr */
- "movl $0x200, %ecx\n\t"
- "xorl %edx, %edx\n\t"
- "movl $(0 | 6), %eax\n\t"
-// "movl $(0 | MTRR_TYPE_WRBACK), %eax\n\t"
- "wrmsr\n\t"
-
- "movl $0x201, %ecx\n\t"
- "movl $0x0000000f, %edx\n\t"
- "movl $((~(( 0 + 0x100000) - 1)) | 0x800), %eax\n\t"
- "wrmsr\n\t"
-
+ __asm__ volatile (
+ "wrmsr"
+ : /* No outputs */
+ : "c" (0x200), "a" (0 | MTRR_TYPE_WRBACK), "d" (0)
+ );
- /* enable cache */
- "movl %cr0, %eax\n\t"
- "andl $0x9fffffff,%eax\n\t"
- "movl %eax, %cr0\n\t"
- "invd\n\t"
+ __asm__ volatile (
+ "wrmsr"
+ : /* No outputs */
+ : "c" (0x201), "a" ((~(( 0 + (CONFIG_LB_MEM_TOPK<<10) ) -1)) | 0x800), "d" (0x0000000f)
+ );
+ __asm__ volatile (
+ /* enable cache */
+ "movl %cr0, %eax\n\t"
+ "andl $0x9fffffff,%eax\n\t"
+ "movl %eax, %cr0\n\t"
+ "invd\n\t"
);
}