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authorYinghai Lu <yinghailu@gmail.com>2006-10-04 20:46:15 +0000
committerYinghai Lu <yinghailu@gmail.com>2006-10-04 20:46:15 +0000
commitd4b278c02c1da92219ebeb34204b9768934aeca3 (patch)
tree488d097cac9744cfc9b8ff7c89ce69bcb21370cb /src/cpu/amd/car
parent2e3757d11c565a8fe68dc2a2c34975e98304533c (diff)
downloadcoreboot-d4b278c02c1da92219ebeb34204b9768934aeca3.tar.xz
AMD Rev F support
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2435 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/amd/car')
-rw-r--r--src/cpu/amd/car/cache_as_ram.inc47
-rw-r--r--src/cpu/amd/car/copy_and_run.c60
-rw-r--r--src/cpu/amd/car/post_cache_as_ram.c34
3 files changed, 119 insertions, 22 deletions
diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc
index 1cf141230b..58570167a9 100644
--- a/src/cpu/amd/car/cache_as_ram.inc
+++ b/src/cpu/amd/car/cache_as_ram.inc
@@ -17,7 +17,7 @@
cache_as_ram_setup:
/* hope we can skip the double set for normal part */
-#if USE_FALLBACK_IMAGE == 1
+#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE==1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE==1))
/* check if cpu_init_detected */
movl $MTRRdefType_MSR, %ecx
rdmsr
@@ -56,16 +56,32 @@ clear_fixed_var_mtrr_out:
wrmsr
movl $0x269, %ecx
wrmsr
-#else
+#endif
- #if CacheSize == 0x8000
+#if CacheSize == 0xc000
+ /* enable caching for 16K using fixed mtrr */
+ movl $0x268, %ecx /* fix4k_c4000*/
+ movl $0x06060606, %edx /* WB IO type */
+ xorl %eax, %eax
+ wrmsr
+ /* enable caching for 32K using fixed mtrr */
+ movl $0x269, %ecx /* fix4k_c8000*/
+ movl $0x06060606, %eax /* WB IO type */
+ movl %eax, %edx
+ wrmsr
+
+#endif
+
+
+#if CacheSize == 0x8000
/* enable caching for 32K using fixed mtrr */
movl $0x269, %ecx /* fix4k_c8000*/
movl $0x06060606, %eax /* WB IO type */
movl %eax, %edx
wrmsr
- #else
+#endif
+#if CacheSize < 0x8000
/* enable caching for 16K/8K/4K using fixed mtrr */
movl $0x269, %ecx /* fix4k_cc000*/
#if CacheSize == 0x4000
@@ -79,8 +95,6 @@ clear_fixed_var_mtrr_out:
#endif
xorl %eax, %eax
wrmsr
- #endif
-
#endif
/* enable memory access for first MBs using top_mem */
@@ -88,9 +102,10 @@ clear_fixed_var_mtrr_out:
xorl %edx, %edx
movl $(((CONFIG_LB_MEM_TOPK << 10) + TOP_MEM_MASK) & ~TOP_MEM_MASK) , %eax
wrmsr
-#endif /* USE_FALLBACK_IMAGE == 1*/
+#endif /* USE_FAILOVER_IMAGE == 1*/
+
-#if USE_FALLBACK_IMAGE == 0
+#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 0)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE==0))
/* disable cache */
movl %cr0, %eax
orl $(0x1<<30),%eax
@@ -108,12 +123,12 @@ clear_fixed_var_mtrr_out:
wrmsr
movl $0x203, %ecx
- movl $0x0000000f, %edx /* AMD 40 bit */
+ movl $((1<<(CPU_ADDR_BITS-32))-1), %edx /* AMD 40 bit */
movl $(~(XIP_ROM_SIZE - 1) | 0x800), %eax
wrmsr
#endif /* XIP_ROM_SIZE && XIP_ROM_BASE */
-#if USE_FALLBACK_IMAGE == 1
+#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE==1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE==1))
/* Set the default memory type and enable fixed and variable MTRRs */
movl $MTRRdefType_MSR, %ecx
xorl %edx, %edx
@@ -133,23 +148,25 @@ clear_fixed_var_mtrr_out:
andl $0x9fffffff,%eax
movl %eax, %cr0
-#if USE_FALLBACK_IMAGE == 1
+#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE==1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE==1))
/* Read the range with lodsl*/
cld
movl $CacheBase, %esi
movl $(CacheSize>>2), %ecx
- rep lodsl
+ rep
+ lodsl
/* Clear the range */
movl $CacheBase, %edi
movl $(CacheSize>>2), %ecx
xorl %eax, %eax
- rep stosl
+ rep
+ stosl
-#endif /*USE_FALLBACK_IMAGE == 1*/
+#endif /*USE_FAILOVER_IMAGE == 1*/
/* set up the stack pointer */
- movl $(CacheBase+CacheSize - 4 - GlobalVarSize), %eax
+ movl $(CacheBase+CacheSize - GlobalVarSize), %eax
movl %eax, %esp
/* Restore the BIST result */
diff --git a/src/cpu/amd/car/copy_and_run.c b/src/cpu/amd/car/copy_and_run.c
index 76b8a8b847..7471a53076 100644
--- a/src/cpu/amd/car/copy_and_run.c
+++ b/src/cpu/amd/car/copy_and_run.c
@@ -2,7 +2,6 @@
moved from nrv2v.c and some lines from crt0.S
2006/05/02 - stepan: move nrv2b to an extra file.
*/
-
static inline void print_debug_cp_run(const char *strval, uint32_t val)
{
#if CONFIG_USE_INIT
@@ -46,8 +45,13 @@ static void copy_and_run(void)
print_debug_cp_run("src=",(uint32_t)src);
print_debug_cp_run("dst=",(uint32_t)dst);
- olen = unrv2b(src, dst);
+// dump_mem(src, src+0x100);
+
+ olen = unrv2b(src, dst, &ilen);
+ print_debug_cp_run("linxbios_ram.nrv2b length = ", ilen);
+
#endif
+// dump_mem(dst, dst+0x100);
print_debug_cp_run("linxbios_ram.bin length = ", olen);
@@ -61,3 +65,55 @@ static void copy_and_run(void)
);
}
+
+#if CONFIG_AP_CODE_IN_CAR == 1
+
+static void copy_and_run_ap_code_in_car(unsigned ret_addr)
+{
+ uint8_t *src, *dst;
+ unsigned long ilen, olen;
+
+// print_debug("Copying LinuxBIOS AP code to CAR.\r\n");
+
+#if !CONFIG_COMPRESS
+ __asm__ volatile (
+ "leal _liseg_apc, %0\n\t"
+ "leal _iseg_apc, %1\n\t"
+ "leal _eiseg_apc, %2\n\t"
+ "subl %1, %2\n\t"
+ : "=a" (src), "=b" (dst), "=c" (olen)
+ );
+ memcpy(dst, src, olen);
+#else
+
+ __asm__ volatile (
+ "leal _liseg_apc, %0\n\t"
+ "leal _iseg_apc, %1\n\t"
+ : "=a" (src) , "=b" (dst)
+ );
+
+// print_debug_cp_run("src=",(uint32_t)src);
+// print_debug_cp_run("dst=",(uint32_t)dst);
+
+// dump_mem(src, src+0x100);
+
+ olen = unrv2b(src, dst, &ilen);
+// print_debug_cp_run("linxbios_apc.nrv2b length = ", ilen);
+
+#endif
+// dump_mem(dst, dst+0x100);
+
+// print_debug_cp_run("linxbios_apc.bin length = ", olen);
+
+// print_debug("Jumping to LinuxBIOS AP code in CAR.\r\n");
+
+ __asm__ volatile (
+ "movl %0, %%ebp\n\t" /* cpu_reset for hardwaremain dummy */
+ "cli\n\t"
+ "leal _iseg_apc, %%edi\n\t"
+ "jmp *%%edi\n\t"
+ :: "a"(ret_addr)
+ );
+
+}
+#endif
diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c
index 0a91326b85..813745d66e 100644
--- a/src/cpu/amd/car/post_cache_as_ram.c
+++ b/src/cpu/amd/car/post_cache_as_ram.c
@@ -18,12 +18,13 @@ static void inline __attribute__((always_inline)) memcopy(void *dest, const voi
{
__asm__ volatile(
"cld\n\t"
- "rep movsl\n\t"
+ "rep; movsl\n\t"
: /* No outputs */
: "S" (src), "D" (dest), "c" ((bytes)>>2)
);
}
+
static void post_cache_as_ram(void)
{
@@ -49,24 +50,34 @@ static void post_cache_as_ram(void)
#error "You need to set CONFIG_LB_MEM_TOPK greater than 1024"
#endif
- set_init_ram_access();
+ set_init_ram_access(); /* So we can access RAM from [1M, CONFIG_LB_MEM_TOPK) */
+// dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x8000, DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x7c00);
print_debug("Copying data from cache to ram -- switching to use ram as stack... ");
/* from here don't store more data in CAR */
+#if 0
__asm__ volatile (
"pushl %eax\n\t"
);
- memcopy((CONFIG_LB_MEM_TOPK<<10)-DCACHE_RAM_SIZE, DCACHE_RAM_BASE, DCACHE_RAM_SIZE); //inline
+#endif
+
+ memcopy((void *)((CONFIG_LB_MEM_TOPK<<10)-DCACHE_RAM_SIZE), (void *)DCACHE_RAM_BASE, DCACHE_RAM_SIZE); //inline
+// dump_mem((CONFIG_LB_MEM_TOPK<<10) - 0x8000, (CONFIG_LB_MEM_TOPK<<10) - 0x7c00);
+
__asm__ volatile (
/* set new esp */ /* before _RAMBASE */
"subl %0, %%ebp\n\t"
"subl %0, %%esp\n\t"
::"a"( (DCACHE_RAM_BASE + DCACHE_RAM_SIZE)- (CONFIG_LB_MEM_TOPK<<10) )
); // We need to push %eax to the stack (CAR) before copy stack and pop it later after copy stack and change esp
+#if 0
__asm__ volatile (
"popl %eax\n\t"
);
+#endif
+
+
/* We can put data to stack again */
/* only global variable sysinfo in cache need to be offset */
@@ -77,14 +88,27 @@ static void post_cache_as_ram(void)
disable_cache_as_ram_bsp();
print_debug("Clearing initial memory region: ");
- clear_init_ram(); //except the range from [(CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_SIZE, (CONFIG_LB_MEM_TOPK<<10)), that is used as stack in ram
+ clear_init_ram(); //except the range from [(CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_SIZE, (CONFIG_LB_MEM_TOPK<<10))
print_debug("Done\r\n");
+// dump_mem((CONFIG_LB_MEM_TOPK<<10) - 0x8000, (CONFIG_LB_MEM_TOPK<<10) - 0x7c00);
+
+#ifndef MEM_TRAIN_SEQ
+#define MEM_TRAIN_SEQ 0
+#endif
+ set_sysinfo_in_ram(1); // So other core0 could start to train mem
+
+#if MEM_TRAIN_SEQ == 1
+// struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE);
+
+ // wait for ap memory to trained
+// wait_all_core0_mem_trained(sysinfox); // moved to lapic_init_cpus.c
+#endif
/*copy and execute linuxbios_ram */
copy_and_run();
/* We will not return */
- print_debug("should not be here -\r\n");
+ print_debug("should not be here -\r\n");
}