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authorElyes HAOUAS <ehaouas@noos.fr>2018-10-31 08:06:12 +0100
committerPatrick Georgi <pgeorgi@google.com>2018-11-05 09:05:51 +0000
commit1a5f1c89d752bf906f7428f96c5ff624a1baba97 (patch)
tree80527bf5c4b6168a59513ee5a1ed7957201d263d /src/cpu/amd/car
parentd35c7fe1bff55471c62b11d208cf3a71dec30d6d (diff)
downloadcoreboot-1a5f1c89d752bf906f7428f96c5ff624a1baba97.tar.xz
cpu/amd: Use common AMD's MSR
This Phase #2 follows the CL done on Phase #1 (Change-Id: I0236e0960cd) Change-Id: Ia296e1f9073b45c9137d17fbef29ce4fdfabcb7c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29369 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/amd/car')
-rw-r--r--src/cpu/amd/car/cache_as_ram.inc8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc
index 7cbf1dbcbb..e4c2704727 100644
--- a/src/cpu/amd/car/cache_as_ram.inc
+++ b/src/cpu/amd/car/cache_as_ram.inc
@@ -415,26 +415,26 @@ fam10_mtrr_setup_complete:
jmp_if_not_fam15h(fam15_car_msr_setup_complete)
/* Disable streaming store (DisSS = 1) */
- mov $0xc0011020, %ecx
+ mov $LS_CFG_MSR, %ecx
rdmsr
bts $28, %eax
wrmsr
/* Disable speculative ITLB reloads (DisSpecTlbRld = 1) */
- mov $0xc0011021, %ecx
+ mov $IC_CFG_MSR, %ecx
rdmsr
bts $9, %eax
wrmsr
/* Disable speculative DTLB reloads (DisSpecTlbRld = 1) and set DisHwPf = 1 */
- mov $0xc0011022, %ecx
+ mov $DC_CFG_MSR, %ecx
rdmsr
bts $4, %eax
bts $13, %eax
wrmsr
/* Disable CR0 combining (CombineCr0Cd = 0) */
- mov $0xc001102b, %ecx
+ mov $BU_CFG3_MSR, %ecx
rdmsr
btr $49-32, %edx
wrmsr