diff options
author | Yinghai Lu <yinghailu@gmail.com> | 2005-12-14 02:39:33 +0000 |
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committer | Yinghai Lu <yinghailu@gmail.com> | 2005-12-14 02:39:33 +0000 |
commit | 72ee9b0ebefa98e05867712eb303269836ec69b4 (patch) | |
tree | 7d732c54abe754f14f1e1e5d93df302b1e04318f /src/cpu/amd/car | |
parent | f42e1770f968adbb4d197917d130219d193081a3 (diff) | |
download | coreboot-72ee9b0ebefa98e05867712eb303269836ec69b4.tar.xz |
issue 51 and 52: set mtrr for ap before stop it, and _RAMBASE above 1M
support and pgtbl after 1M support
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2142 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/amd/car')
-rw-r--r-- | src/cpu/amd/car/clear_1m_ram.c | 40 | ||||
-rw-r--r-- | src/cpu/amd/car/post_cache_as_ram.c | 10 |
2 files changed, 43 insertions, 7 deletions
diff --git a/src/cpu/amd/car/clear_1m_ram.c b/src/cpu/amd/car/clear_1m_ram.c index d4c6600247..c61610ff64 100644 --- a/src/cpu/amd/car/clear_1m_ram.c +++ b/src/cpu/amd/car/clear_1m_ram.c @@ -69,3 +69,43 @@ static inline __attribute__((always_inline)) void clear_1m_ram(void) #endif ); } + +/* be warned, this file will be used by core other than core 0/node 0 or core0/node0 when cpu_reset*/ +static inline __attribute__((always_inline)) void set_1m_ram(void) +{ + __asm__ volatile ( + + /* disable cache */ + "movl %%cr0, %%eax\n\t" + "orl $(0x1<<30),%%eax\n\t" + "movl %%eax, %%cr0\n\t" + + /* enable caching for first 1M using variable mtrr */ + "movl $0x200, %%ecx\n\t" + "xorl %%edx, %%edx\n\t" + "movl $(0 | 6), %%eax\n\t" +// "movl $(0 | MTRR_TYPE_WRBACK), %%eax\n\t" + "wrmsr\n\t" + + "movl $0x201, %%ecx\n\t" + "movl $0x0000000f, %%edx\n\t" +#if CONFIG_USE_INIT + "movl %%esi, %%eax\n\t" +#else + "movl $((~(( 0 + (CONFIG_LB_MEM_TOPK<<10) ) -1)) | 0x800), %%eax\n\t" +#endif + "wrmsr\n\t" + + /* enable cache */ + "movl %%cr0, %%eax\n\t" + "andl $0x9fffffff,%%eax\n\t" + "movl %%eax, %%cr0\n\t" +// "invd\n\t" // Is the BSP done with mem init? + : + : +#if CONFIG_USE_INIT + "S"((~(( 0 + (CONFIG_LB_MEM_TOPK<<10) ) -1)) | 0x800) +#endif + ); +} + diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index fec5905822..345e4c34b0 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -48,13 +48,9 @@ static void post_cache_as_ram(unsigned cpu_reset) if(cpu_reset==0) { // cpu_reset don't need to clear it clear_1m_ram(); } - -#if 0 - int i; - for(i=0;i<0x800000;i++) { - outb(0x66, 0x80); + else { + set_1m_ram(); } -#endif __asm__ volatile ( /* set new esp */ /* before _RAMBASE */ @@ -63,7 +59,7 @@ static void post_cache_as_ram(unsigned cpu_reset) ::"a"( (DCACHE_RAM_BASE + DCACHE_RAM_SIZE)- _RAMBASE ) ); - { + { unsigned new_cpu_reset; /* get back cpu_reset from ebx */ |