CAR patch from YH LU

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2096 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

5 files changed, 188 insertions, 151 deletions

diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc
index dfa2b03ac3..b8ec1ca407 100644
--- a/src/cpu/amd/car/cache_as_ram.inc
+++ b/src/cpu/amd/car/cache_as_ram.inc
@@ -8,10 +8,17 @@
 
 	/* Save the BIST result */
 	movl    %eax, %ebp
+	
+	// for normal part %ebx already contain cpu_init_detected from fallback call
 
 CacheAsRam:
 	/* hope we can skip the double set for normal part */
 #if USE_FALLBACK_IMAGE == 1
+
+	movl	$MTRRdefType_MSR, %ecx
+	rdmsr
+	andl $0x00000800, %eax
+	movl %eax, %ebx ;  // We store the status about if cpu_init_detected
 	
 	/* Set MtrrFixDramModEn for clear fixed mtrr */
 	xorl	%eax, %eax			# clear %eax and %edx
@@ -53,7 +60,6 @@ clear_fixed_var_mtrr_out:
         orl     $(SYSCFG_MSR_MtrrVarDramEn | SYSCFG_MSR_MtrrFixDramEn), %eax
         wrmsr
 
-#if 1
 #if CacheSize == 0x10000 
         /* enable caching for 64K using fixed mtrr */
         movl    $0x268, %ecx  /* fix4k_c0000*/
@@ -86,30 +92,6 @@ clear_fixed_var_mtrr_out:
 	xorl    %eax, %eax
 	wrmsr
 
-#else
-        /* enable caching for 64K using variable mtrr */
-        movl    $0x200, %ecx
-        xorl    %edx, %edx
-        movl     $(CacheBase | MTRR_TYPE_WRBACK), %eax
-        wrmsr
-
-        movl    $0x201, %ecx
-        movl    $0x0000000f, %edx /* AMD 40 bit 0xff*/
-        movl    $((~((CacheBase + CacheSize) - 1)) | 0x800), %eax
-        wrmsr  
-	
-	/* make it to be IO by clearing RD Dram and WR Dram */
-	movl    $IORR0_BASE, %ecx
-        xorl    %edx, %edx
-        movl    $CacheBase, %eax             /* bit 3, and bit 4 = 0 mean clear RD ram and WR ram */
-        wrmsr
-
-        movl    $IORR0_MASK, %ecx
-        movl    $0x000000ff, %edx
-        movl    $(~((CacheBase + CacheSize) - 1) | 0x800), %eax
-        wrmsr 
-#endif
-
         /* enable memory access for 0 - 1MB using top_mem */
         movl    $TOP_MEM, %ecx
         xorl    %edx, %edx
@@ -145,7 +127,6 @@ clear_fixed_var_mtrr_out:
 
 #if USE_FALLBACK_IMAGE == 1
 
-
         /* Read the range with lodsl*/
         movl    $(CacheBase+CacheSize-4), %esi
         std
@@ -157,36 +138,6 @@ clear_fixed_var_mtrr_out:
         xorl    %eax, %eax
         rep     stosl
 
-#if 0
-	/* check the cache as ram */
-	movl  $CacheBase, %esi
-	movl    $(CacheSize>>2), %ecx
-.xin1:
-	movl  %esi, %eax
-	movl  %eax, (%esi)
-        movl    $0x1000, %edx
-	movb	%ah, %al
-.testx1:  
-        outb %al, $0x80
-        decl    %edx
-	jnz .testx1
-
-	movl  (%esi), %eax
-	cmpb 0xff, %al
-	je .xin2  /* dont show */
-        movl    $0x1000, %edx
-.testx2:
-        outb %al, $0x80
-        decl    %edx
-        jnz .testx2
-
-.xin2:	decl     %ecx
-        je      .xout1
-        add     $4, %esi
-        jmp     .xin1
-.xout1:
-
-#endif
 #endif /*USE_FALLBACK_IMAGE == 1*/
 
 
@@ -198,6 +149,7 @@ clear_fixed_var_mtrr_out:
 	movl    %ebp, %eax
 	/* We need to set ebp ? No need */
 	movl	%esp, %ebp
+	pushl %ebx  /* init detected */
 	pushl %eax  /* bist */
 	call    amd64_main
 	/* We will not go back */
diff --git a/src/cpu/amd/car/cache_as_ram_post.c b/src/cpu/amd/car/cache_as_ram_post.c
index 6a129b258a..e69de29bb2 100644
--- a/src/cpu/amd/car/cache_as_ram_post.c
+++ b/src/cpu/amd/car/cache_as_ram_post.c
@@ -1,95 +0,0 @@
-/* by yhlu 6.2005 */
-/* be warned, this file will be used other cores and core0/node0 */
-        __asm__ volatile (
-	/* 
-	FIXME : backup stack in CACHE_AS_RAM into mmx and sse and after we get STACK up, we restore that.
-		It is only needed if we want to go back
-	*/
-	
-        /* We don't need cache as ram for now on */
-        /* disable cache */
-        "movl    %cr0, %eax\n\t"
-        "orl    $(0x1<<30),%eax\n\t"
-        "movl    %eax, %cr0\n\t"
-
-        /* clear sth */
-        "movl    $0x269, %ecx\n\t"  /* fix4k_c8000*/
-        "xorl    %edx, %edx\n\t"
-        "xorl    %eax, %eax\n\t"
-	"wrmsr\n\t"
-#if DCACHE_RAM_SIZE > 0x8000
-	"movl    $0x268, %ecx\n\t"  /* fix4k_c0000*/
-        "wrmsr\n\t"
-#endif
-
-        /* disable fixed mtrr from now on, it will be enabled by linuxbios_ram again*/
-        "movl    $0xC0010010, %ecx\n\t"
-//        "movl    $SYSCFG_MSR, %ecx\n\t"
-        "rdmsr\n\t"
-        "andl    $(~(3<<18)), %eax\n\t"
-//        "andl    $(~(SYSCFG_MSR_MtrrFixDramModEn | SYSCFG_MSR_MtrrFixDramEn)), %eax\n\t"
-        "wrmsr\n\t"
-
-        /* Set the default memory type and disable fixed and enable variable MTRRs */
-        "movl    $0x2ff, %ecx\n\t"
-//        "movl    $MTRRdefType_MSR, %ecx\n\t"
-        "xorl    %edx, %edx\n\t"
-        /* Enable Variable and Disable Fixed MTRRs */
-        "movl    $0x00000800, %eax\n\t"
-        "wrmsr\n\t"
-
-#if defined(CLEAR_FIRST_1M_RAM)
-        /* enable caching for first 1M using variable mtrr */
-        "movl    $0x200, %ecx\n\t"
-        "xorl    %edx, %edx\n\t"
-        "movl     $(0 | 1), %eax\n\t"
-//	"movl     $(0 | MTRR_TYPE_WRCOMB), %eax\n\t"
-        "wrmsr\n\t"
-
-        "movl    $0x201, %ecx\n\t"
-        "movl    $0x0000000f, %edx\n\t" 
-        "movl    $((~(( 0 + 0x100000) - 1)) | 0x800), %eax\n\t"
-        "wrmsr\n\t"
-#endif
-
-        /* enable cache */
-        "movl    %cr0, %eax\n\t"
-        "andl    $0x9fffffff,%eax\n\t"
-        "movl    %eax, %cr0\n\t"
-#if defined(CLEAR_FIRST_1M_RAM)
-        /* clear the first 1M */
-        "movl    $0x0, %edi\n\t"
-        "cld\n\t"
-        "movl    $(0x100000>>2), %ecx\n\t"
-        "xorl    %eax, %eax\n\t"
-        "rep     stosl\n\t"
-
-        /* disable cache */
-        "movl    %cr0, %eax\n\t"
-        "orl    $(0x1<<30),%eax\n\t"
-        "movl    %eax, %cr0\n\t"
-
-        /* enable caching for first 1M using variable mtrr */
-        "movl    $0x200, %ecx\n\t"
-        "xorl    %edx, %edx\n\t"
-        "movl     $(0 | 6), %eax\n\t"
-//	"movl     $(0 | MTRR_TYPE_WRBACK), %eax\n\t"
-        "wrmsr\n\t"
-
-        "movl    $0x201, %ecx\n\t"
-        "movl    $0x0000000f, %edx\n\t" 
-        "movl    $((~(( 0 + 0x100000) - 1)) | 0x800), %eax\n\t"
-        "wrmsr\n\t"
-
-        /* enable cache */
-        "movl    %cr0, %eax\n\t"
-        "andl    $0x9fffffff,%eax\n\t"
-        "movl    %eax, %cr0\n\t"
-	"invd\n\t"
-
-	/* 
-	FIXME: I hope we don't need to change esp and ebp value here, so we can restore value from mmx sse back
-		But the problem is the range is some io related, So don't go back
-	*/
-#endif
-        );
diff --git a/src/cpu/amd/car/clear_1m_ram.c b/src/cpu/amd/car/clear_1m_ram.c
new file mode 100644
index 0000000000..85ba59cf73
--- /dev/null
+++ b/src/cpu/amd/car/clear_1m_ram.c
@@ -0,0 +1,53 @@
+/* by yhlu 6.2005 */
+/* be warned, this file will be used core 0/node 0 only */
+        __asm__ volatile (
+
+        /* disable cache */
+        "movl    %cr0, %eax\n\t"
+        "orl    $(0x1<<30),%eax\n\t"
+        "movl    %eax, %cr0\n\t"
+
+        /* enable caching for first 1M using variable mtrr */
+        "movl    $0x200, %ecx\n\t"
+        "xorl    %edx, %edx\n\t"
+        "movl     $(0 | 1), %eax\n\t"
+//	"movl     $(0 | MTRR_TYPE_WRCOMB), %eax\n\t"
+        "wrmsr\n\t"
+
+        "movl    $0x201, %ecx\n\t"
+        "movl    $0x0000000f, %edx\n\t" 
+        "movl    $((~(( 0 + 0x100000) - 1)) | 0x800), %eax\n\t"
+        "wrmsr\n\t"
+
+        /* clear the first 1M */
+        "movl    $0x0, %edi\n\t"
+        "cld\n\t"
+        "movl    $(0x100000>>2), %ecx\n\t"
+        "xorl    %eax, %eax\n\t"
+        "rep     stosl\n\t"
+
+        /* disable cache */
+        "movl    %cr0, %eax\n\t"
+        "orl    $(0x1<<30),%eax\n\t"
+        "movl    %eax, %cr0\n\t"
+
+        /* enable caching for first 1M using variable mtrr */
+        "movl    $0x200, %ecx\n\t"
+        "xorl    %edx, %edx\n\t"
+        "movl     $(0 | 6), %eax\n\t"
+//	"movl     $(0 | MTRR_TYPE_WRBACK), %eax\n\t"
+        "wrmsr\n\t"
+
+        "movl    $0x201, %ecx\n\t"
+        "movl    $0x0000000f, %edx\n\t" 
+        "movl    $((~(( 0 + 0x100000) - 1)) | 0x800), %eax\n\t"
+        "wrmsr\n\t"
+
+
+        /* enable cache */
+        "movl    %cr0, %eax\n\t"
+        "andl    $0x9fffffff,%eax\n\t"
+        "movl    %eax, %cr0\n\t"
+	"invd\n\t"
+
+        );
diff --git a/src/cpu/amd/car/disable_cache_as_ram.c b/src/cpu/amd/car/disable_cache_as_ram.c
new file mode 100644
index 0000000000..a699cae99b
--- /dev/null
+++ b/src/cpu/amd/car/disable_cache_as_ram.c
@@ -0,0 +1,46 @@
+/* by yhlu 6.2005 */
+/* be warned, this file will be used other cores and core 0 / node 0 */
+        __asm__ volatile (
+	/* 
+	FIXME : backup stack in CACHE_AS_RAM into mmx and sse and after we get STACK up, we restore that.
+		It is only needed if we want to go back
+	*/
+	
+        /* We don't need cache as ram for now on */
+        /* disable cache */
+        "movl    %cr0, %eax\n\t"
+        "orl    $(0x1<<30),%eax\n\t"
+        "movl    %eax, %cr0\n\t"
+
+        /* clear sth */
+        "movl    $0x269, %ecx\n\t"  /* fix4k_c8000*/
+        "xorl    %edx, %edx\n\t"
+        "xorl    %eax, %eax\n\t"
+	"wrmsr\n\t"
+#if DCACHE_RAM_SIZE > 0x8000
+	"movl    $0x268, %ecx\n\t"  /* fix4k_c0000*/
+        "wrmsr\n\t"
+#endif
+
+        /* disable fixed mtrr from now on, it will be enabled by linuxbios_ram again*/
+        "movl    $0xC0010010, %ecx\n\t"
+//        "movl    $SYSCFG_MSR, %ecx\n\t"
+        "rdmsr\n\t"
+        "andl    $(~(3<<18)), %eax\n\t"
+//        "andl    $(~(SYSCFG_MSR_MtrrFixDramModEn | SYSCFG_MSR_MtrrFixDramEn)), %eax\n\t"
+        "wrmsr\n\t"
+
+        /* Set the default memory type and disable fixed and enable variable MTRRs */
+        "movl    $0x2ff, %ecx\n\t"
+//        "movl    $MTRRdefType_MSR, %ecx\n\t"
+        "xorl    %edx, %edx\n\t"
+        /* Enable Variable and Disable Fixed MTRRs */
+        "movl    $0x00000800, %eax\n\t"
+        "wrmsr\n\t"
+
+        /* enable cache */
+        "movl    %cr0, %eax\n\t"
+        "andl    $0x9fffffff,%eax\n\t"
+        "movl    %eax, %cr0\n\t"
+
+        );
diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c
new file mode 100644
index 0000000000..b78ce77211
--- /dev/null
+++ b/src/cpu/amd/car/post_cache_as_ram.c
@@ -0,0 +1,81 @@
+static void post_cache_as_ram(unsigned cpu_reset)
+{
+
+
+#if 1
+        {
+        /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
+        unsigned v_esp;
+        __asm__ volatile (
+                "movl   %%esp, %0\n\t"
+                : "=a" (v_esp)
+        );
+#if CONFIG_USE_INIT
+        printk_debug("v_esp=%08x\r\n", v_esp);
+#else
+        print_debug("v_esp="); print_debug_hex32(v_esp); print_debug("\r\n");
+#endif
+        }
+#endif
+
+#if CONFIG_USE_INIT
+        printk_debug("cpu_reset = %08x\r\n",cpu_reset);
+#else
+        print_debug("cpu_reset = "); print_debug_hex32(cpu_reset); print_debug("\r\n");
+#endif
+
+        if(cpu_reset == 0) {
+                print_debug("Clearing initial memory region: ");
+        }
+        print_debug("No cache as ram now - ");
+
+        /* store cpu_reset to ebx */
+        __asm__ volatile (
+                "movl %0, %%ebx\n\t"
+                ::"a" (cpu_reset)
+        );
+
+#include "cpu/amd/car/disable_cache_as_ram.c"
+
+        if(cpu_reset==0) { // cpu_reset don't need to clear it 
+#include "cpu/amd/car/clear_1m_ram.c"
+        }
+
+        __asm__ volatile (
+                /* set new esp */ /* before _RAMBASE */
+                "subl   %0, %%ebp\n\t"
+                "subl   %0, %%esp\n\t"
+                ::"a"( (DCACHE_RAM_BASE + DCACHE_RAM_SIZE)- _RAMBASE )
+        );
+
+       {
+                unsigned new_cpu_reset;
+
+                /* get back cpu_reset from ebx */
+                __asm__ volatile (
+                        "movl %%ebx, %0\n\t"
+                        :"=a" (new_cpu_reset)
+                );
+
+                print_debug("Use Ram as Stack now - "); /* but We can not go back any more, we lost old stack data in cache as ram*/
+                if(new_cpu_reset==0) {
+                        print_debug("done\r\n");
+                } else
+                {
+                        print_debug("\r\n");
+                }
+
+#if CONFIG_USE_INIT
+                printk_debug("new_cpu_reset = %08x\r\n", new_cpu_reset);
+#else
+                print_debug("new_cpu_reset = "); print_debug_hex32(new_cpu_reset); print_debug("\r\n");
+#endif
+                /*copy and execute linuxbios_ram */
+                copy_and_run(new_cpu_reset);
+                /* We will not return */
+        }
+
+	print_debug("should not be here -\r\n");
+
+}
+