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author | Furquan Shaikh <furquan@google.com> | 2014-04-22 10:41:05 -0700 |
---|---|---|
committer | Patrick Georgi <patrick@georgi-clan.de> | 2014-04-26 13:27:09 +0200 |
commit | 20f25dd5c8a513ee136e9f6d8c67959591298617 (patch) | |
tree | e42f5cfe77fb4f73d3b8eb759f5faa328997efc8 /src/cpu/amd/car | |
parent | 817149643c27fca022cf526d6113a4aff898d511 (diff) | |
download | coreboot-20f25dd5c8a513ee136e9f6d8c67959591298617.tar.xz |
Rename coreboot_ram stage to ramstage
Rename coreboot_ram stage to ramstage. This is done in order to provide
consistency with other stage names (bootblock, romstage) and to allow any
Makefile rule generalization, required for patches to be submitted later.
Change-Id: Ib66e43b7e17b9c48b2d099670ba7e7d857673386
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/5567
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/cpu/amd/car')
-rw-r--r-- | src/cpu/amd/car/disable_cache_as_ram.c | 2 | ||||
-rw-r--r-- | src/cpu/amd/car/post_cache_as_ram.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/amd/car/disable_cache_as_ram.c b/src/cpu/amd/car/disable_cache_as_ram.c index 24533c7eb9..7776ae7224 100644 --- a/src/cpu/amd/car/disable_cache_as_ram.c +++ b/src/cpu/amd/car/disable_cache_as_ram.c @@ -36,7 +36,7 @@ static inline __attribute__((always_inline)) void disable_cache_as_ram(void) #if CONFIG_DCACHE_RAM_SIZE > 0x8000 wrmsr(MTRRfix4K_C0000_MSR, msr); #endif - /* disable fixed mtrr from now on, it will be enabled by coreboot_ram again*/ + /* disable fixed mtrr from now on, it will be enabled by ramstage again*/ msr = rdmsr(SYSCFG_MSR); msr.lo &= ~(SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_MtrrFixDramModEn); diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index f74f915ec5..97127855be 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -153,7 +153,7 @@ cache_as_ram_new_stack (void *resume_backup_memory __attribute__ ((unused))) set_sysinfo_in_ram(1); // So other core0 could start to train mem - /*copy and execute coreboot_ram */ + /*copy and execute ramstage */ copy_and_run(); /* We will not return */ |