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authorStefan Reinauer <stepan@coresystems.de>2010-07-08 16:41:05 +0000
committerStefan Reinauer <stepan@openbios.org>2010-07-08 16:41:05 +0000
commit6f57b514cb6e0598b295a3d8a4345dd42209e1e6 (patch)
treebb54404f902b1339bdba36523d4ba069628b5532 /src/cpu/amd/car
parent817d7542f708215c4128b6cdc39ca7d7e1256b26 (diff)
downloadcoreboot-6f57b514cb6e0598b295a3d8a4345dd42209e1e6.tar.xz
Fix all warnings in the tree
(does not fix the cmos.layout race yet) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5660 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/amd/car')
-rw-r--r--src/cpu/amd/car/cache_as_ram.inc15
1 files changed, 8 insertions, 7 deletions
diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc
index a14c9f41f5..aedb2fd564 100644
--- a/src/cpu/amd/car/cache_as_ram.inc
+++ b/src/cpu/amd/car/cache_as_ram.inc
@@ -37,16 +37,16 @@
#include <cpu/x86/mtrr.h>
#include <cpu/amd/mtrr.h>
/*
- XMM map:
- xmm1: cpu family
- xmm2: fam10 comparison value
- xmm3: backup ebx
-*/
+ * XMM map:
+ * xmm1: cpu family
+ * xmm2: fam10 comparison value
+ * xmm3: backup ebx
+ */
/* Save the BIST result */
movl %eax, %ebp
- /*for normal part %ebx already contain cpu_init_detected from fallback call */
+ /* for normal part %ebx already contain cpu_init_detected from fallback call */
cache_as_ram_setup:
post_code(0xa0)
@@ -113,7 +113,8 @@ cache_as_ram_setup:
CAR_FAM10_out:
/* Errata 193: Disable clean copybacks to L3 cache to allow cached ROM.
- Re-enable it in after RAM is initialized and before CAR is disabled */
+ * Re-enable it in after RAM is initialized and before CAR is disabled
+ */
movl $0xc001102a, %ecx
rdmsr
bts $15, %eax