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| author | Scott Duplichan <scott@notabs.org> | 2010-09-14 17:28:41 +0000 |
|---|---|---|
| committer | Marc Jones <marc.jones@amd.com> | 2010-09-14 17:28:41 +0000 |
| commit | 9b0c690c09137d85d9c9280ce082094089ee9032 (patch) | |
| tree | 09fc1a7a992ffbc21dc28d4be59632449c6c07ee /src/cpu/amd/car | |
| parent | 3f1d29c408e35d379c85a6c2671401fcc4964e34 (diff) | |
| download | coreboot-9b0c690c09137d85d9c9280ce082094089ee9032.tar.xz | |
This patch corrects a coding error in the original implementation
of 'Erratum 343 for AMD Fam10h CPUs' (rev 4345). The original code
sets msr c001_102a bit 3 when bit 35 was intended.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5814 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/amd/car')
| -rw-r--r-- | src/cpu/amd/car/cache_as_ram.inc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index 218a538c35..e4f1ba426d 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -129,8 +129,8 @@ CAR_FAM10_out: /* execute special read command for msr-register. Result is then in the EDX:EAX-registers (MSBs in EDX) */ rdmsr - /* Set bit 35 to 1 in EAX */ - bts $35, %eax + /* Set bit 35 to 1 in EAX:EDX */ + bts $35-32, %edx /* write back the modified register EDX:EAX to the MSR specified in ECX */ wrmsr |