diff options
| author | Damien Zammit <damien@zamaudio.com> | 2016-11-28 00:29:10 +1100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-01-04 18:56:01 +0100 |
| commit | 75a3d1fb7c31bc5bd287bf6579ff70c5da9275a7 (patch) | |
| tree | 618c2bc04f44cf73d3dae288bff0a5e2ef44d616 /src/cpu/amd/car | |
| parent | 6c20b65849aeda664cc40ebc0f0bab2e99768423 (diff) | |
| download | coreboot-75a3d1fb7c31bc5bd287bf6579ff70c5da9275a7.tar.xz | |
amdfam10: Perform major include ".c" cleanup
Previously, all romstages for this northbridge family
would compile via 1 single C file with everything
included into the romstage.c file (!)
This patch separates the build into separate .o modules
and links them accordingly.
Currently compiles and links all fam10 roms without
breaking other roms.
Both DDR2 and DDR3 have been completed
TESTED on REACTS: passes all boot tests for 2 boards
ASUS KGPE-D16
ASUS KFSN4-DRE
Some extra changes were required to make it compile
otherwise there were unused functions in included "c" files.
This is because I needed to exchange CIMX
for the native southbridge routines. See in particular:
advansus/a785e-i
asus/m5a88-v
avalue/eax-785e
A followup patch may be required to fix the above boards.
See FIXME, XXX tags
Change-Id: Id0f9849578fd0f8b1eab83aed910902c27354426
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/17625
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
Diffstat (limited to 'src/cpu/amd/car')
| -rw-r--r-- | src/cpu/amd/car/disable_cache_as_ram.c | 1 | ||||
| -rw-r--r-- | src/cpu/amd/car/post_cache_as_ram.c | 2 |
2 files changed, 3 insertions, 0 deletions
diff --git a/src/cpu/amd/car/disable_cache_as_ram.c b/src/cpu/amd/car/disable_cache_as_ram.c index 1eb3dd756f..bab464e25e 100644 --- a/src/cpu/amd/car/disable_cache_as_ram.c +++ b/src/cpu/amd/car/disable_cache_as_ram.c @@ -19,6 +19,7 @@ */ #include <cpu/x86/cache.h> +#include <cpu/x86/msr.h> static inline __attribute__((always_inline)) uint32_t amd_fam1x_cpu_family(void) { diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 88b86378bd..efcd111e8f 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -17,11 +17,13 @@ * GNU General Public License for more details. */ #include <string.h> +#include <console/console.h> #include <arch/stages.h> #include <arch/early_variables.h> #include <cpu/x86/mtrr.h> #include <cpu/amd/mtrr.h> #include <cpu/amd/car.h> +#include <cpu/amd/msr.h> #include <arch/acpi.h> #include <romstage_handoff.h> #include "cbmem.h" |