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| author | Patrick Georgi <patrick@georgi-clan.de> | 2012-03-31 12:52:21 +0200 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-04-25 16:27:07 +0200 |
| commit | 05e740fc40e409dcf8d592f4bbeaf87dc92140c5 (patch) | |
| tree | 5b05e1ea6cd2a9c82ac218984e8ee5526c9b77c5 /src/cpu/amd/car | |
| parent | 8919729307028746cf7bc527ca511183fe3b401b (diff) | |
| download | coreboot-05e740fc40e409dcf8d592f4bbeaf87dc92140c5.tar.xz | |
Replace cache control magic numbers with symbols
Instead of opaque numbers like (1<<29), use
symbols like CR0_NoWriteThrough.
Change-Id: Id845e087fb472cfaf5f71beaf37fbf0d407880b5
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/833
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/cpu/amd/car')
| -rw-r--r-- | src/cpu/amd/car/cache_as_ram.inc | 3 | ||||
| -rw-r--r-- | src/cpu/amd/car/disable_cache_as_ram.c | 4 |
2 files changed, 5 insertions, 2 deletions
diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index 4625da1ca0..18a19fc030 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -19,6 +19,7 @@ */ #include <cpu/x86/mtrr.h> +#include <cpu/x86/cache.h> #include <cpu/amd/mtrr.h> #define CacheSize CONFIG_DCACHE_RAM_SIZE @@ -320,7 +321,7 @@ wbcache_post_fam10_setup: /* Enable cache. */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 jmp_if_k8(fam10_end_part1) diff --git a/src/cpu/amd/car/disable_cache_as_ram.c b/src/cpu/amd/car/disable_cache_as_ram.c index 0f91154824..a48a39c6ab 100644 --- a/src/cpu/amd/car/disable_cache_as_ram.c +++ b/src/cpu/amd/car/disable_cache_as_ram.c @@ -21,12 +21,14 @@ * be warned, this file will be used other cores and core 0 / node 0 */ +#include <cpu/x86/cache.h> + static inline __attribute__((always_inline)) void disable_cache_as_ram(void) { msr_t msr; /* disable cache */ - write_cr0(read_cr0() | (1 << 30)); + write_cr0(read_cr0() | CR0_CacheDisable); msr.lo = 0; msr.hi = 0; |